Breakthrough Performance and Integration
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The Virtex™ UltraScale+™ VU19P FPGA enables prototyping and emulation of the most advanced ASIC and SoC technologies, as well as the development of complex algorithms. The VU19P FPGA provides the highest logic density and I/O count on a single device ever built by AMD, addressing new classes of demands in evolving technologies.
9 million system logic cells allow designers to emulate and prototype larger-scale, more complex designs, and create customized test logic for test-equipment vendors.
Massive I/O bandwidth is not only ideal for multi-FPGA interconnect but also allows engineers to connect a broad range of external memory types and rates to implement fast, deep storage of state information.
80 GTY (28Gb/s) transceivers offer up to 4.5Tb/s transceiver bandwidth, which is suited for high port density test equipment and next-generation platforms using emerging interface standards and protocols.
Lidless packaging provides an optimal cooling solution that allows designers to push the limits of performance to the extreme. Deploying high-performance systems in the thermally-constrained environment is now easier than ever.
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As complexity grows in ASICs and SoCs, extensive verification before tape-out is a must. While massive 9 million system logic cells enable customers to implement larger designs, over 2000 I/Os allow customers to store state information, which is very critical for design visibility and debugging.
16nm Virtex UltraScale+ FPGA performance enables accurate system modeling and fast verification of targeted designs. While the VU19P enables real I/O traffic, Vivado™ Design Suite and AMD tools allow developers to bring-up software and implement custom features before physical part availability.
Massive logic capacity and high-speed transceivers offer room to implement customized test logic and new protocols while enabling higher port density in the same footprint. The cooling solution allows next-gen test equipment to push the performance envelope to the extreme in the thermally constrained environment.
|System Logic Cells (K)
|PCIe® Gen3 x 16/Gen4x8/CCIX
|GTY/GTM Transceivers (32.75/58Gb/s)||80/0|
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