Zynq™ UltraScale+™ MPSoC

Heterogeneous Multiprocessing Platform for Broad Range of Embedded Applications

Product Advantages

Scalable Portfolio of Adaptable MPSoCs

Zynq UltraScale+ MPSoC Block Diagram

Zynq™ UltraScale+™ MPSoC devices provide 64-bit processor scalability while combining real-time control with soft and hard engines for graphics, video, waveform, and packet processing. Built on a common real-time processor and programmable logic equipped platform, three distinct variants include dual application processor (CG) devices, quad application processor and GPU (EG) devices, and video codec (EV) devices, creating unlimited possibilities for applications such as 5G Wireless, Next-generation ADAS, and Industrial Internet-of-Things.

Zynq UltraScale+ CG

Dual-core Entry Point to Heterogeneous Processing

  • Dual Arm® Cortex®-A53
  • Dual Arm Cortex-R5F
  • 16nm FinFET+ Programmable Logic

Zynq UltraScale+ EG

Broad Device Range for Next-Generation Applications

  • Quad Arm Cortex-A53
  • Dual Arm Cortex-R5F
  • 16nm FinFET+ Programmable Logic
  • Arm Mali™-400MP2

Zynq UltraScale+ EV

Video Codec Enabled for Multimedia and Embedded Vision

  • Quad Arm Cortex-A53
  • Dual Arm Cortex-R5F
  • 16nm FinFET+ Programmable Logic
  • Arm Mali-400MP2
  • H.264/H.265 Video Codec
Heterogeneous Processing for Whole Application Acceleration


Heterogeneous Processing for Whole Application Acceleration

Multiple processing engines enable the optimization of functions across an entire application, with programmable hardware providing further performance and safety handling.

Ultra-Compact Packages for Unmatched Compute Density


Ultra-Compact Packages for High Compute Density

InFO devices are 60% smaller, 70% thinner, with better thermal dissipation and higher signal integrity, all without sacrificing the processing power of the Zynq UltraScale+ MPSoC.

Integrated H.264 / H.265 Video Codec


Integrated H.264 / H.265 Video Codec
 

Zynq UltraScale+ EV devices include a video codec capable of low latency simultaneous encode and decode up to 4K resolution at 60 frames per second.

Deep Learning Processing Unit for AI / ML


Deep Learning Processing Unit for AI / ML
 

Free scalable computation engine optimized for convolutional neural networks, supporting common frameworks, leveraging large repositories of pre-trained AI models.

Adaptable Memory Hierarchy Removes Memory Bottlenecks


Adaptable Memory Hierarchy Addresses Memory Bottlenecks

Vast distributed on-chip memory: LUTRAM, Block RAM, UltraRAM, L3 Cache, minimizing memory access latency and allowing accelerators or co-processors to achieve maximum performance. Localized memory also allows full function isolation necessary for safety critical applications.

Multiple Domains for Granular Power Management


Multiple Domains for Granular Power Management

Flexible architecture capable of reducing power consumption by eliminating static power of unused blocks, for up to 30% less1 static power consumption. Operate as low as 180nW in full Deep Sleep mode for maximum power savings when idle.

Footnote:
1. ZUS-007. See “Managing Power and Performance with the Zynq UltraScale+ MP SOC” whitepaper, page 7.

Product Table

Zynq UltraScale+ CG

Dual-core Entry Point to Heterogeneous Processing

Zynq UltraScale+ EG

Broad Device Range for Next-Generation Applications

Zynq UltraScale+ EV

Video Codec Enabled for Multimedia and Embedded Vision

Zynq UltraScale+ MPSoC CG Devices

CG Devices

Processing System Features

  ZU1CG ZU2CG ZU3CG ZU3T ZU4CG ZU5CG ZU6CG ZU7CG ZU9CG
Application Processing Unit Dual-core Arm® Cortex®-A53 MPCore™ up to 1.3GHz
Real-Time Processing Unit  Dual-core Arm Cortex-R5F MPCore up to 533MHz
Dynamic Memory Interface DDR4, LPDDR4, DDR3, DDR3L, LPDDR3
High-Speed Peripherals PCIe® Gen2, USB3.0, SATA 3.1, DisplayPort, Gigabit Ethernet

Programmable Logic

  ZU1CG ZU2CG ZU3CG ZU3T ZU4CG ZU5CG ZU6CG ZU7CG ZU9CG
System Logic Cells (K) 81 103 154 157 192 256 469 504 600
Total RAM (Mb)* 4.8 6.5 9.4 21.2 20.6 26.6 32 44.2 40.9
DSP Slices 216 240 360 576 728 1,248 1,973 1,728 2,520
16.3 Gb/s Transceiver Count - - - 8 16
16 24
24 24
PCI Express - - - 1x Gen3x8 2x Gen3x8 or
1x Gen3x16
2x Gen3x8 or
1x Gen3x16
- 1x Gen3x16 and
1x Gen3x8
-
Maximum I/O Pins 180 252 252 124 252 252 328 464 328

* Total RAM= Maximum Distributed RAM + Total Block RAM + UltraRAM

Zynq UltraScale+ MPSoC EG Devices

EG Devices

Processing System Features

  ZU1EG ZU2EG ZU3EG ZU3T ZU4EG ZU5EG ZU6EG ZU7EG ZU9EG ZU11EG ZU15EG ZU17EG ZU19EG
Application Processing Unit Quad-core Arm® Cortex®-A53 MPCore™ up to 1.5GHz
Real-Time Processing Unit Dual-core Arm Cortex-R5F MPCore™ up to 600MHz
Graphics Processing Unit Arm Mali™-400 MP2 up to 667MHz
Dynamic Memory Interface DDR4, LPDDR4, DDR3, DDR3L, LPDDR3
High-Speed Peripherals PCIe® Gen2, USB3.0, SATA 3.1, DisplayPort, Gigabit Ethernet

Programmable Logic

  ZU1EG ZU2EG ZU3EG ZU3T ZU4EG ZU5EG ZU6EG ZU7EG ZU9EG ZU11EG ZU15EG ZU17EG ZU19EG
System Logic Cells (K) 81 103 154 157 192 256 469 504 600 653 747 926 1,143
Total RAM (Mb)* 4.8 6.5 9.4 21.2 20.6 26.6 32 44.2 40.9 52.7 69 64.7 80.4
DSP Slices 216 240 360 576 728 1,248 1,973 1,728 2,520 2,928 3,528 1,590 1,968
16.3 Gb/s Transceivers - - - 8 16 16 24 24 24 32 24 44 44
32.75 Gb/s Transceivers - - - - - - - - - 16 - 28 28
PCI Express - - - 1x Gen3x8 2x Gen3x8 or 1x Gen3x16 2x Gen3x8 or 1x Gen3x16 - 1x Gen3x16 and
1x Gen3x8
- 2x Gen3x16 or
4x Gen3x8
- (2x Gen3x16 and 1x Gen3x8) or
4x Gen3x8
(2x Gen3x16 and 1x Gen3x8) or
5x Gen3x8
Maximum I/O Pins 180 252 252 124 252 252 328 464 328 512 328 668 668

* Total RAM= Maximum Distributed RAM + Total Block RAM + UltraRAM

Zynq UltraScale+ MPSoC EV Devices

EV Devices

Processing System Features

  ZU4EV ZU5EV ZU7EV
Application Processing Unit Quad-core Arm® Cortex®-A53 MPCore™ up to 1.5GHz
Real-Time Processing Unit Dual-core Arm Cortex-R5F MPCore™ up to 600MHz
Graphics Processing Unit Arm Mali™-400 MP2 up to 667MHz
Video Codec Unit Supports H.264 / H.265
Dynamic Memory Interface DDR4, LPDDR4, DDR3, DDR3L, LPDDR3
High-Speed Peripherals PCIe® Gen2, USB3.0, SATA 3.1, DisplayPort, Gigabit Ethernet

Programmable Logic

  ZU4EV ZU5EV ZU7EV
System Logic Cells (K) 192 256 504
Total RAM (Mb)* 20.6 26.6 44.2
DSP Slices 728 1,248 1,728
Video Code Unit (VCU) 1 1 1
Maximum I/O Pins 252 252 464

* Total RAM= Maximum Distributed RAM + Total Block RAM + UltraRAM

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