The JESD204B interface standard supports the high bandwidth necessary to keep pace with today’s leading high performance, high speed and multi-channel applications, while greatly reducing the number of digital IOs needed and thus easing board layout. Very high-speed ADCs that would have previously required a complex interface design using a large number of FPGA IO are now implemented with just a few pins.  The total bandwidth of the JESD204B interface can also be separated into multiple channels based on the requirements of the application again without requiring additional pins.