We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 10004

4.1i FPGA Editor - Trace reports no errors, but the history window reports a number of errors.


Keywords: FPGA Editor, 3.1i, Trace, error, TRCE

Urgency: Standard

General Description:
When I run Trace in FPGA Editor, the Error Report summary contains no errors, but the history window reports a number of errors.


The problem arises because a timing constraint is placed before a DLL. A timing constraint that is placed before the DLL is pushed through the DLL, but is manipulated depending upon which pin is being used.

For example, if you have a 100 MHz period on CLKIN, and use a DIVIDE output of 4, the tools will create a new constraint that is a 25 MHz period for this signal. However, this is done by the timing tool; thus, it is not in the PCF file.

This means when FPGA Editor opens the design, it is only aware of the input constraint. As there are no synchronous - synchronous paths in this signal, it reports "0 items analyzed."

However, there really are "X" number of timing errors, as will be shown if the Timing Analyzer is run.

To work around this, you can add a the constraint to the PCF; this will explicitly include the period on the output of the DLL, so FPGA Editor will take this into account when analyzing the design. Please note that the modified PCF should not be used when running through PAR, as it will most likely fail. This modified PCF should only be used to view constraints through the FPGA Editor. For regular implementation, use the original PCF file output from MAP.

Example of PCF modification:

NET "clk_ibuf/IBUFG" PERIOD = 13.333 nS HIGH 50.000 % ;
//This constraint reports 0 items analyzed, because it is the input into a DLL

NET "clk_c" PERIOD = 13.333 nS HIGH 50.000 % ;

This constraint places a period constraint on the output of the DLL. In this case, the 0X output is used. To find the specific net upon which to place this constraint, use FPGA Editor and select the DLL instance. Then, find the output net name and constrain that
path with the appropriate constraint.
AR# 10004
Date 10/08/2003
Status Archive
Type General Article