# AR# 10019

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## Description

How do I apply a PERIOD constraint to my design?

## Solution

Basic Period Specification

Figure 1 - Basic Period Specification

The PERIOD constraint covers only paths between synchronous elements. Synchronous elements include FFs, LATCHs, and Synch RAMs (PADS are not synchronous elements). An example of the UCF specification is as follows:

NET CLK PERIOD = 20 ns;

Example of the constraint in the timing report:

==============================================================

Timing constraint: NET "CLK" PERIOD = 20 nS HIGH 50.000 % ;

1 item analyzed, 0 timing errors detected.

Minimum period is 3.109ns.

----------------------------------------------------------------------------------------------------------------------------

For more details on timing constraints, please see the Timing Constraints User Guide:
http://www.xilinx.com/support/documentation/sw_manuals/xilinx12_1/ug612.pdf

PERIOD Using TIMESPEC Keyword

Figure 2 - Period Using TIMESPEC

Another way to write the previous PERIOD constraint is to use the TIMESPEC keyword. (This is the preferred method for describing clocks.) In the following example, the TNM creates a user-defined group, and the TIMESPEC defines the timing specifications on that group.

NOTE: TIMESPEC names must begin with "TS".

NET CLK TNM = SYSCLK;

TIMESPEC TS_SYSCLK = PERIOD SYSCLK 20;

Example of the constraint in the timing report:

===============================================================

Timing constraint: TS_SYSCLK = PERIOD TIMEGRP "SYSCLK" 20 nS HIGH 50.000 % ;

1 item analyzed, 0 timing errors detected.

Minimum period is 3.109ns.

-----------------------------------------------------------------------------------------------------------------------------

Duty Cycle and PERIOD

Figure 3 - Duty Cycle and Period

Examples of the original PERIOD Constraint and a PERIOD constraint with a 25% duty cycle

Example 1

UCF Specification:

NET CLK PERIOD = 20 HIGH 5;

==================================================

Timing constraint: NET "CLK" PERIOD = 20 nS HIGH 5 nS ;

1 item analyzed, 0 timing errors detected.

Minimum period is 3.109ns.

---------------------------------------------------------------------------------------------------

Example 1

UCF Specification;

NET CLK TNM = SYSCLK;

TIMESPEC TS_SYSCLK = PERIOD SYSCLK 20 LOW 5;

Example of the constraint in the timing report:

================================================================

Timing constraint: TS_SYSCLK = PERIOD TIMEGRP "SYSCLK" 20 nS LOW 5 nS ;

1 item analyzed, 0 timing errors detected.

Minimum period is 3.109 ns.

------------------------------------------------------------------------------------------------------------------------------

Rising/Falling Edge Clocks

Figure 4 - Rising/Falling Edge Clocks

UCF Specification:

NET CLK PERIOD = 20 ns;

Example of the constraint in the timing report:

=================================================================

Timing constraint: NET "CLK" PERIOD = 20 nS HIGH 50.000 % ;

1 item analyzed, 0 timing errors detected.

Minimum period is 6.218ns.

---------------------------------------------------------------------------------------------------------------------------------

Slack:

6.891ns path \$Net00004_ to DATA_OUT relative to

3.106ns total path delay

0.003ns clock skew

10.000ns delay constraint (two-phase clock)

--------------------------------------------------------------------------------

NOTES:

1. The minimum period is doubled (it was previously 3.109 ns).

2. The allotted time for the clock period was cut in half.

3. The phrase "two-phase clock" demonstrates that it was automatically recognized.

DLL CLK0 and Period

Figure 5 - DLL CLK0 and Period

UCF Specification:

NET "CLKIN" TNM_NET = "CLKIN";

TIMESPEC "TS_CLKIN" = PERIOD "CLKIN" 20 ns HIGH 50 %;

================================================================================

Timing constraint: TS_CLK0 = PERIOD TIMEGRP "clk0" TS_CLKIN * 1.000000 HIGH 50.000 % ;

1 item analyzed, 0 timing errors detected. (0 setup errors, 0 hold errors)

Minimum period is 1.296ns.

--------------------------------------------------------------------------------

Slack: 18.704ns (requirement - (data path - clock skew))

Source: ff_clk01 (FF)

Destination: ff2_clk01 (FF)

Requirement: 20.000ns

Data Path Delay: 1.296ns (Levels of Logic = 0)

Clock Skew: 0.000ns

Source Clock: clk0_bufg rising at 0.000ns

Destination Clock: clk0_bufg rising at 20.000ns

Note that the PERIOD transferred to the DLL clock output.

DLL CLK2X and Period

Figure 6 - DLL CLK2X and Period

UCF Specification:

NET "CLKIN" TNM_NET = "CLKIN";

TIMESPEC "TS_CLKIN" = PERIOD "CLKIN" 20 ns HIGH 50 %;

================================================================================

Timing constraint: TS_clk2x_dll = PERIOD TIMEGRP "clk2x_dll" TS_clkin / 2.000000 HIGH 50.000 % ;

1 item analyzed, 0 timing errors detected. (0 setup errors, 0 hold errors)

Minimum period is 1.304ns.

--------------------------------------------------------------------------------

Slack: 8.696ns (requirement - (data path - clock skew))

Source: ff_clk01 (FF)

Destination: ff2_clk01 (FF)

Requirement: 10.000ns

Data Path Delay: 1.304ns (Levels of Logic = 0)

Clock Skew: 0.000ns

Source Clock: clk2x_dll_bufg rising at 0.000ns

Destination Clock: clk2x_dll_bufg rising at 10.000ns

Note that the PERIOD was transferred and cut in half.

CLKDV and Period

Figure 7 - DLL CLKDV and Period

UCF Specification:

INST MYDLL CLKDV_DIVIDE = 2.5;

NET "CLKIN" TNM_NET = "CLKIN";

TIMESPEC "TS_CLKIN" = PERIOD "CLKIN" 20 ns HIGH 50 %;

================================================================================

Timing constraint: TS_clkdv_dll = PERIOD TIMEGRP "clkdv_dll" TS_clkin * 2.500000 HIGH 50.000 % ;

1 item analyzed, 0 timing errors detected. (0 setup errors, 0 hold errors)

Minimum period is 1.304ns.

--------------------------------------------------------------------------------

Slack: 48.696ns (requirement - (data path - clock skew))

Source: ff_clk01 (FF)

Destination: ff2_clk01 (FF)

Requirement: 50.000ns

Data Path Delay: 1.304ns (Levels of Logic = 0)

Clock Skew: 0.000ns

Source Clock: clkdv_dll_bufg rising at 0.000ns

Destination Clock: clkdv_dll_bufg rising at 50.000ns

NOTE: The DLL must be fed back from CLK0 or CLK2X through BUFG.
AR# 10019
Date 01/24/2013
Status Active
Type General Article
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