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AR# 10026

3.1i Virtex MAP - RAM/SRL16E packed with latch results in bad clock inversion.


Keywords: RAM, SRL16, latch, inverted, inversion, inverter, clock clk

Urgency: Standard

General Description:
When a latch is packed with a RAM or SRL16E, the clock input is inverted for both;
this is incorrect for the RAM/SRL16E.


A workaround is to use map constraints to prevent the unwanted pack.
The easiest way to do this would be to apply a unique XBLKNM attribute
to the problem latch.

Sample UCF syntax:

INST "latch_inst_name" XBLKNM = XLNX_WA ;

This will prevent the latch from from being packed with any other comps. If there are
other comps that need to be packed into the same slice with the latch, they should be
assigned the same XBLKNM attribute.

This problem is fixed in the latest 3.1i Service Pack available at:
http://support.xilinx.com/support/techsup/sw_updates. The first
service pack containing the fix is 3.1i Service Pack 4.
AR# 10026
Date 08/19/2002
Status Archive
Type General Article