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  3. AR# 10028: 3.1i Virtex MAP - ERROR: "Pack:679 - Unable to obey design constraints ..."

AR# 10028

3.1i Virtex MAP - ERROR: "Pack:679 - Unable to obey design constraints ..."

Description

Keywords: ERROR:Pack:679, LUT, FLOP, pack, connectivity, restrictions

Urgency: Standard

General Description:
MAP displays the following error, declaring that the LUT/FLOP combination is unpackable:

ERROR:Pack:679 - Unable to obey design constraints (LOC = CLB_R47C98.S0) which
require the combination of the following symbols into a single slice
component:
FLOP symbol "port1_euo/igs_insrt_inst/O_DATA[23]" (Output Signal =
port1_euo/s_data_2_0(23))
LUT symbol "port1_euo/G_203" (Output Signal = port1_euo/G_203)
LUT symbol "port1_euo/G_239" (Output Signal = port1_euo/o_data_7(23))
FLOP symbol "port1_euo/igs_insrt_inst/O_SOC" (Output Signal =
port1_euo/s_soc_2)
Unable to pack the register because of connectivity restrictions. Please
correct the design constraints accordingly.

Solution

1

This problem is fixed in the latest 3.1i Service Pack available at:
http://support.xilinx.com/support/techsup/sw_updates. The first
service pack containing the fix is 3.1i Service Pack 3.

2

A variation of this error message has been seen when unconnected I/Os existed in
the user's HDL code.
AR# 10028
Date 08/19/2002
Status Archive
Type General Article
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