entity DRAM is port ( RAM_DATA, WRITE_EN, RAM0_IN, RAM1_IN, RAM2_IN, RAM3_IN: in STD_LOGIC; RAM_OUT: out STD_LOGIC ); end DRAM;
architecture XILINX of DRAM is
-- Distributed RAM component RAM16X1 port ( D : in std_ulogic; WE : in std_ulogic; A0 : in std_ulogic; A1 : in std_ulogic; A2 : in std_ulogic; A3 : in std_ulogic; O : out std_ulogic); end component;
attribute INIT: string; attribute INIT of RAM_EXAMPLE: label is "ABAC";
begin RAM_EXAMPLE : RAM16X1 port map ( O => RAM_OUT, WE => WRITE_EN, D => RAM_DATA, A0 => RAM0_IN, A1 => RAM1_IN, A2 => RAM2_IN, A3 => RAM3_IN );
end XILINX;
-- VHDL Example for ROM library IEEE; use IEEE.std_logic_1164.all;
entity DROM is port ( ROM0_IN, ROM1_IN, ROM2_IN, ROM3_IN: in STD_LOGIC; ROM_OUT: out STD_LOGIC ); end DROM;
architecture XILINX of DROM is
-- Distributed ROM component ROM16X1 port (A0 : in std_ulogic; A1 : in std_ulogic; A2 : in std_ulogic; A3 : in std_ulogic; O : out std_ulogic ); end component;
attribute INIT: string; attribute INIT of ROM_EXAMPLE: label is "10A7";
begin ROM_EXAMPLE : ROM16X1 port map( O => ROM_OUT, A0 => ROM0_IN, A1 => ROM1_IN, A2 => ROM2_IN, A3 => ROM3_IN );