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  3. AR# 10073: FPGA Express 3.4 - How do I instantiate and initialize RAM or ROM in HDL?

AR# 10073

FPGA Express 3.4 - How do I instantiate and initialize RAM or ROM in HDL?

Description

Keywords: Synopsys, FPGA Express, instanitate, RAM, ROM, initialize, VHDL, Verilog

Urgency: Standard

General Description:
How do I instantiate and initialize RAM or ROM using Synopsys' FPGA Express?

For more specifics on RAM and ROM primitives, please see the following links:

http://toolbox.xilinx.com/docsan/3_1i/data/common/lib/chap09/lib09003.htm
http://toolbox.xilinx.com/docsan/3_1i/data/common/lib/chap09/lib09029.htm

NOTE: Tested with FPGA Express 3.4

Solution

1

Verilog Example of RAM

module RAM_EXAMPLE (O, A0, A1, A2, A3, D, WE);
output O;
input A0, A1, A2, A3, D, WE;

RAM16X1 U1 (.O(O), .A0(A0), .A1(A1), .A2(A2), .A3(A3), .D(D), .WE(WE));
//synopsys attribute INIT "ABAC"

endmodule

//Verlog Example of ROM

module ROM_EXAMPLE (O, A0, A1, A2, A3);
output O;
input A0, A1, A2, A3;

ROM16X1 U1 (.O(O), .A0(A0), .A1(A1), .A2(A2), .A3(A3));
//synopsys attribute INIT "10A7"

endmodule

2

VHDL Example for RAM

library IEEE;
use IEEE.std_logic_1164.all;

entity DRAM is
port ( RAM_DATA, WRITE_EN, RAM0_IN, RAM1_IN, RAM2_IN, RAM3_IN: in STD_LOGIC;
RAM_OUT: out STD_LOGIC
);
end DRAM;

architecture XILINX of DRAM is

-- Distributed RAM
component RAM16X1
port ( D : in std_ulogic;
WE : in std_ulogic;
A0 : in std_ulogic;
A1 : in std_ulogic;
A2 : in std_ulogic;
A3 : in std_ulogic;
O : out std_ulogic);
end component;

attribute INIT: string;
attribute INIT of RAM_EXAMPLE: label is "ABAC";

begin
RAM_EXAMPLE : RAM16X1 port map (
O => RAM_OUT,
WE => WRITE_EN,
D => RAM_DATA,
A0 => RAM0_IN,
A1 => RAM1_IN,
A2 => RAM2_IN,
A3 => RAM3_IN
);

end XILINX;

-- VHDL Example for ROM
library IEEE;
use IEEE.std_logic_1164.all;

entity DROM is
port ( ROM0_IN, ROM1_IN, ROM2_IN, ROM3_IN: in STD_LOGIC;
ROM_OUT: out STD_LOGIC
);
end DROM;

architecture XILINX of DROM is

-- Distributed ROM
component ROM16X1
port (A0 : in std_ulogic;
A1 : in std_ulogic;
A2 : in std_ulogic;
A3 : in std_ulogic;
O : out std_ulogic
);
end component;

attribute INIT: string;
attribute INIT of ROM_EXAMPLE: label is "10A7";

begin
ROM_EXAMPLE : ROM16X1 port map(
O => ROM_OUT,
A0 => ROM0_IN,
A1 => ROM1_IN,
A2 => ROM2_IN,
A3 => ROM3_IN
);


end XILINX;
AR# 10073
Date 08/11/2003
Status Archive
Type General Article

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