General Description: Because RAM cannot currently be inferred with FPGA Express, it is necessary to instantiate any RAM primitive that will be needed. How do I instantiate and initialize Virtex Select Block RAM for synthesis (Synopsys' FPGA Express) and simulation?
--synopsys translate_off; library unisim; use unisim.vcomponents.all; --synopsys translate_on;
entity RAMB is port (RAMB_DATA : in STD_LOGIC_VECTOR (7 downto 0); ADDRESS : in STD_LOGIC_VECTOR (8 downto 0); ENABLE, WRITE, RESET, CLOCK : in STD_LOGIC; RAMB_OUT : out STD_LOGIC_VECTOR (7 downto 0) ); end RAMB;
architecture XILINX of RAMB is
-- Block RAM
component RAMB4_S8 port (DI : in STD_LOGIC_VECTOR (7 downto 0); EN : in STD_ULOGIC; WE : in STD_ULOGIC; RST : in STD_ULOGIC; CLK : in STD_ULOGIC; ADDR : in STD_LOGIC_VECTOR (8 downto 0); DO : out STD_LOGIC_VECTOR (7 downto 0)); end component;
attribute INIT_00 of RAMB_EXAMPLE : label is "1F1E1D1C1B1A191817161514131211100F0E0D0C0B0A09080706050403020100"; attribute INIT_01 of RAMB_EXAMPLE : label is "1F1E1D1C1B1A191817161514131211100F0E0D0C0B0A09080706050403020100"; : :
begin
RAMB_EXAMPLE: RAMB4_S8
-- The generic maps in this example are for simulation only --synopsys translate_off GENERIC MAP ( INIT_00 => X"1F1E1D1C1B1A191817161514131211100F0E0D0C0B0A09080706050403020100",
// The defparam in this example are for simulation only //synopsys translate_off defparam RAMB_EXAMPLE.INIT_00 = 256'h1F1E1D1C1B1A191817161514131211100F0E0D0C0B0A09080706050403020100; defparam RAMB_EXAMPLE.INIT_01 = 256'h1F1E1D1C1B1A191817161514131211100F0E0D0C0B0A09080706050403020100; : :