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  3. AR# 10076: 3.x FPGA Express - How do I instantiate and initialize Virtex Select Block RAM?

AR# 10076

3.x FPGA Express - How do I instantiate and initialize Virtex Select Block RAM?

Description

Keywords: FPGA Express, Synopsys, instantiate, block, RAM, select, initialize

Urgency: Standard

General Description:
Because RAM cannot currently be inferred with FPGA Express, it is necessary to instantiate any RAM primitive that will be needed. How do I instantiate and initialize Virtex Select Block RAM for synthesis (Synopsys' FPGA Express) and simulation?

(For more information on Block RAM, please refer to the Libraries Guide:
http://support.xilinx.com/support/library.htm )

NOTE: Tested with FPGA Express 3.4 and newer

Solution

1

VHDL Example:

library IEEE;
use IEEE.std_logic_1164.all;

--synopsys translate_off;
library unisim;
use unisim.vcomponents.all;
--synopsys translate_on;

entity RAMB is
port (RAMB_DATA : in STD_LOGIC_VECTOR (7 downto 0);
ADDRESS : in STD_LOGIC_VECTOR (8 downto 0);
ENABLE, WRITE, RESET, CLOCK : in STD_LOGIC;
RAMB_OUT : out STD_LOGIC_VECTOR (7 downto 0)
);
end RAMB;

architecture XILINX of RAMB is

-- Block RAM

component RAMB4_S8
port (DI : in STD_LOGIC_VECTOR (7 downto 0);
EN : in STD_ULOGIC;
WE : in STD_ULOGIC;
RST : in STD_ULOGIC;
CLK : in STD_ULOGIC;
ADDR : in STD_LOGIC_VECTOR (8 downto 0);
DO : out STD_LOGIC_VECTOR (7 downto 0));
end component;

attribute INIT_00: string;
attribute INIT_01: string;
:
:

attribute INIT_00 of RAMB_EXAMPLE : label is "1F1E1D1C1B1A191817161514131211100F0E0D0C0B0A09080706050403020100";
attribute INIT_01 of RAMB_EXAMPLE : label is "1F1E1D1C1B1A191817161514131211100F0E0D0C0B0A09080706050403020100";
:
:

begin

RAMB_EXAMPLE: RAMB4_S8

-- The generic maps in this example are for simulation only
--synopsys translate_off
GENERIC MAP (
INIT_00 => X"1F1E1D1C1B1A191817161514131211100F0E0D0C0B0A09080706050403020100",

INIT_01 => X"1F1E1D1C1B1A191817161514131211100F0E0D0C0B0A09080706050403020100",
:
:

)

--synopsys translate_on

port map(
DI => RAMB_DATA,
EN => ENABLE,
WE => WRITE,
RST => RESET,
CLK => CLOCK,
ADDR => ADDRESS,
DO => RAMB_OUT
);

end XILINX;

2

Verilog Example:

module RAMB (DO, ADDR, DI, EN, CLK, WE, RST);
output [7:0] DO;
input [8:0] ADDR;
input [7:0] DI;
input EN, CLK, WE, RST;

// The defparam in this example are for simulation only
//synopsys translate_off
defparam RAMB_EXAMPLE.INIT_00 = 256'h1F1E1D1C1B1A191817161514131211100F0E0D0C0B0A09080706050403020100;
defparam RAMB_EXAMPLE.INIT_01 = 256'h1F1E1D1C1B1A191817161514131211100F0E0D0C0B0A09080706050403020100;
:
:

//synopsys translate_on

RAMB4_S8 RAMB_EXAMPLE (.DO(DO), .ADDR(ADDR), .DI(DI), .EN(EN), .CLK(CLK), .WE(WE), .RST(RST));

/*synopsys attribute
INIT_00 "1F1E1D1C1B1A191817161514131211100F0E0D0C0B0A09080706050403020100"
INIT_01 "FEDCBA9876543210FEDCBA9876543210FEDCBA9876543210FEDCBA9876543210"
:
:

*/

endmodule
AR# 10076
Date 08/11/2003
Status Archive
Type General Article