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5.1i ISE - VHDL Source code - "Create symbol" fails with "ERROR: This design does not contain an entity named my_design ..."
Keywords: VHDL, create, symbol, check, syntax
My VHDL source code passes the "Check syntax" command; however, the "Create symbol" process fails with the message:
"ERROR: This design does not contain an entity named <my_design> ..."
The "Create symbol" process parses the entire VHDL file, including the comments. If the comments contain invalid characters, the parser will fail.
To avoid this problem, remove the characters from the file.
The "Check syntax" utility does not check the commented lines, so the problem does not occur when this utility is executed.
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