General Description: The "vhdl_analyze_order" file and "verilog_analyze_order" files delivered with the D_IP1 update do not contain a complete list of VHDL and Verilog models that are available for behavior model compilation.
"Vhdl_analyze_order" and "verilog_analyze_order" files can be found respectively in:
Some of the behavior models missing from the analyze order files are: vfft_utils.vhd trigtabl_v1_0.vhd trigtabl_v1_0_comp.vhd mult_vgen_v1_0.vhd mult_vgen_v1_0_comp.vhd da_fir_v1_0.vhd da_fir_v1_0_comp.vhd dafir_pack.vhd async_fifo_pkg.vhd async_fifo_v1_0.vhd async_fifo_v1_0_comp.vhd
(The same files are missing from the Verilog list.There may be others that have not yet been discovered.)
These files were delivered with the original release of 3.1i, and they are still valid to use with the D_IP1 update. If you have installed the D_IP1 update over 3.1i software from your CD, you will still be able to use the above behavioral models. (They were missing only from the "analyze_order files" list delivered with D_IP1.
If you have already compiled the XilinxCoreLib using the "analyze_order_file," it is likely that the files missing from the list have not been compiled at all.
If you cannot download the new IP update, you can run "get_models" and generate the new "analyze_order" files yourself. However, we recommend that you download the new IP update, as it will also fix other issues.
In order to generate new "analyze_order" files, use the "get_models" utility. "Get_models" utility will extract all the behavior models available from the xilinx/coregen/ip/... tree. It will then generate the complete list of models it was able to extract.
To run get_models, type following at a Unix or DOS prompt:
>get_models -vhdl -dest <directory_to_exract_models> or >get_models -verilog -dest <directory_to_extract_models>
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AR# 10118
Date
08/23/2002
Status
Archive
Type
General Article
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