AR# 10127


3.4 FPGA Express - Falling edge flip-flop is not using a negative flip-flop.


Keywords: FPGA Express, 3.4, 3.3, falling, edge, clock, not, using, negative, flip, flop,
inverting, global, clock, F2.1i, F3.1i

Urgency: Standard

General Description:
A design with positive and negative edge flip-flops may use an FMAP/LUT as
an inverter to invert the clock signal instead of correctly using the "free"
inverter for clocks on flip-flops.

To use a "free" inverter, the Xilinx primitive INV needs to be inferred by the
synthesis tool instead of inferring an FMAP/LUT with programming information.


Starting with version 3.5, FPGA Express will now use the INV primitive for 4K
designs. Virtex designs no longer exhibit this problem. Please see
(Xilinx Solution 11068) for more FPGA Express issues with negative edge flip-flops.
AR# 10127
Date 08/21/2002
Status Archive
Type General Article
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