AR# 10130


6.1 System Generator for DSP - Can I generate Verilog HDL code?


Keywords: MathWorks, MATLAB, Simulink, SysGen, token

When I use the System Generator token to generate my Xilinx design, I see only VHDL code being generated. Can I generate Verilog code?


Starting with System Generator for DSP 6.3, you can now generate Verilog Code.

The System Generator for DSP Users Guide lists the limitations of Verilog Netlisting.
AR# 10130
Date 07/18/2007
Status Archive
Type General Article
People Also Viewed