UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 10134

System Generator for DSP - Is it possible to pass user-defined constraints into the generated VHDL?

Description

General Description:

Is it possible to pass user-defined constraints into the generated VHDL?

Solution

No -- there is no current mechanism for passing user-defined constraints into the generated VHDL.

Was this Answer Record helpful?

AR# 10134
Date	05/14/2014
Status	Archive
Type	General Article

Page Bookmarked