AR# 10134

System Generator for DSP - Is it possible to pass user-defined constraints into the generated VHDL?

Description

General Description: 

Is it possible to pass user-defined constraints into the generated VHDL?

Solution

No -- there is no current mechanism for passing user-defined constraints into the generated VHDL.

AR# 10134
Date 05/14/2014
Status Archive
Type General Article