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AR# 10134

System Generator for DSP - Is it possible to pass user-defined constraints into the generated VHDL?

Description

General Description: 

Is it possible to pass user-defined constraints into the generated VHDL?

Solution

No -- there is no current mechanism for passing user-defined constraints into the generated VHDL.

AR# 10134
Date Created 08/29/2007
Last Updated 05/14/2014
Status Archive
Type General Article