AR# 10157


3.1i SP2 CORE Generator - VHDL Viewlogic schematic core generation fails with: "Viewlogic symbol generation failed"


Keywords: CORE Generator, COREGen, Viewlogic, 3.1, SP2, schematic, VHDL, VHX, symbol, eProduct

Urgency: Standard

General Description:
When I generate a CORE Generator module for Viewlogic schematics in VHDL, the generator reports the following errors and warnings:

ERROR: Elaboration of core Asynchronous_FIFO failed.
ERROR: Viewlogic symbol generation failed. Check vllink.log for errors.
ERROR: Core myfifo3 did not generate Viewlogic .VHX symbol generation support file.
WARNING: Warnings and/or errors encountered while generating myfifo3 (Asynchronous_FIFO 1.0) All output products requested may not have been generated.
ERROR: Elaboration failure for core Asynchronous_FIFO

(NOTE: For Viewlogic EPD ver. 1.0, please see Resolution 2 for additional modifications. Older version of Viewlogic are excluded.)



CORE Generator generates a VHX file that Viewlogic uses to create a symbol. The .vhx file contains a VHDL entity that has been incorrectly generated.

To correct this problem, modifiy the last I/O declaration. A close-parenthesis symbol ")" must be inserted at the end of the last I/O declaration before the semi-colon:

An example .vhx file:

entity test is
port (
clk : in std_logic;
din : in_std_logic_vector(15 downto 0);
dout : out_std_logic_vector(15 downto 0);
empty : out std_logic;
end test;

"empty : out std_logic;" <=== changed this line to
"empty : out std_logic);" <=== add ")".


Viewlogic EPD ver. 1.0

The Viewlogic file "vhdl2sym.bat" uses the VHX file to create a symbol. This bat file is called "vhdl2sym.exe".

vhdl2sym.bat resides in the path: ePD\1.0\common\win32\bin
vhdl2sym.exe resides in ePD\1.0\wv\1999.2\win32\bin

You will need to move vhdl2sym.exe to the same directory where vhdl2sym.bat is located before the steps in Resolution 1 will work.
AR# 10157
Date 08/23/2002
Status Archive
Type General Article
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