General Description: My design contains an instantiated module and an associated configuration statement. If I run "View VHDL Instantiation Template" or "View VHDL Test Bench Template," Project Navigator returns the following error message:
FATAL ERROR: VHDL Analyzer suffered an internal error. Description of the error is: top_ram.vhd(72): Construct 'mark : sel_name' is not currently supported. Please contact technical support... top_ram.vhd(70): WARNING: Configurations are currently ignored. ERROR: This design does not contain an entity named top_ram... vhdtdtfi completed with errors...
A workaround is to comment out the configuration statement when running "View VHDL Instantiation Template" or "View VHDL Test Bench Template."
This is necessary because the parser does not understand the "Synopsys Translate Off" and "Synopsys Translate On" directives.