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AR# 10167

14.x Timing - Does Timing Analyzer account for the output jitter of the DCM/DLL/PLL/MMCMs? (Clock Uncertainty)

Description

Does Timing Analyzer account for the output jitter of the DCM/DLL/PLL/MMCMs?

Solution

DCM/PLL/MMCM jitter and phase errors are taken into account in the timing report for Virtex-4, Virtex-5, and Virtex-6 devices as Clock Uncertainty. No DCM jitter will be analyzed or reported for legacy device families that do not have characterized DCM jitter.
AR# 10167
Date Created 08/29/2007
Last Updated 12/15/2012
Status Active
Type General Article
Tools
  • ISE Design Suite - 12.1
  • ISE Design Suite - 12.2
  • ISE Design Suite - 12.3
  • More
  • ISE Design Suite - 12.4
  • ISE Design Suite - 13
  • ISE Design Suite - 13.1
  • ISE Design Suite - 13.2
  • ISE Design Suite - 13.3
  • ISE Design Suite - 13.4
  • ISE Design Suite - 14.1
  • Less