AR# 10167: 14.x Timing - Does Timing Analyzer account for the output jitter of the DCM/DLL/PLL/MMCMs? (Clock Uncertainty)
AR# 10167
14.x Timing - Does Timing Analyzer account for the output jitter of the DCM/DLL/PLL/MMCMs? (Clock Uncertainty)
Description
Does Timing Analyzer account for the output jitter of the DCM/DLL/PLL/MMCMs?
Solution
DCM/PLL/MMCM jitter and phase errors are taken into account in the timing report for Virtex-4, Virtex-5, and Virtex-6 devices as Clock Uncertainty. No DCM jitter will be analyzed or reported for legacy device families that do not have characterized DCM jitter.