UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!
Page Bookmarked
  1. Xilinx - All Programmable
  2. Support
  3. AR# 10256: 3.1i Virtex-E PAR - Problem with DLLIOB "SelectIO" input and placement

AR# 10256

3.1i Virtex-E PAR - Problem with DLLIOB "SelectIO" input and placement

Description

Keywords: DLLIOB, SelectIO, placer, placement

Urgency: Standard

General Description:
When the DLLIOB uses the FastFeedback pin, it should act as an input. If
the DLLIOB uses a "SelectIO" STD, it is not being seen as an input; consequently,
the placement is incorrectly allowing other I/Os into the VREF sites. The problem
is caught by the general DRC of PAR.

Solution

A workaround is to lock the I/O.

This problem is fixed in the latest 3.1i Service Pack available at:
http://support.xilinx.com/support/techsup/sw_updates. The first
service pack containing the fix is 3.1i Service Pack 4.
AR# 10256
Date 10/21/2008
Status Archive
Type General Article