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WebPACK 3.1i XST - Pin locks are not picked up correctly or are in the wrong order when "pin_assign" attribute is used
When I use the "pin_assign" attribute in VHDL on a range of pins, the software appears to ignore the constraints and places the pins in arbitrary locations.
This was fixed in the 4.1i software.
The following work-around can be used for earlier software versions:
Check to see if the bus is a non-standard range [e.g., (15 downto 8)], for an 8-bit bus. If so, you have two options:
1. Change the port definition so that it is (7 downto 0).
2. Add 8 "dummy" pins for the non-existent lower 8 bits. These pin constraints will not be used; only the last 8 will be.
attribute pin_assign of AH: signal is "p1 p1 p1 p1 p1 p1 p1 p1 p23 p22 p21 p20 p19 p18 p16 p14";
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