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AR# 10382

3.1i COREGEN - Known Issues in the 3.1i IP Update #2 or Update#2a (D_IP2a).

Description

Keywords: D_IP2, 32i_ip_update2, Release Note, COREGen, DA, FIR, filter, sine, cosine,
lut, lookup, table, Virtex, adder, subtracter, FD, based, shift, register, accumulator, Virtex-II,
block, RAM, memory, problem, single-port, dual-port, block memory, Asynchronous FIFO,
release notes, distributor memory, FFT, 32i_ip_update_2a, CORE Generator

Urgency: Standard

General Description:
This answer record addresses known issues in 32i_ip_update2a. (This is also referred to as D_IP2a).
This IP update replaces the original release of 32i_ip_update2, which was released in November, 2000.
The newer version (_2a) will address the issue noted in (Xilinx Answer #10853).

Solution

GENERAL KNOWN ISSUES

-----------------------------------
Software Compatibility
-----------------------------------
The D_IP2a IP update is only compatible with Xilinx CORE Generator v3.1i, which is included
with Alliance v3.1i, Foundation v3.1i, and Foundation ISE v3.1i software. This IP update is also
compatible with v3.2i and v3.3i as well. This IP update should not be used with any other versions
of CORE Generator (such as v2.1i or earlier).

NOTE: Some data sheets may still refer to these cores as being compatible with v2.1i; however,
this information is incorrect and will be updated in the next release.

------------------------------------------
Service Pack Requirement
------------------------------------------
D_IP2a has been tested with Xilinx software v3.1i and Service Pack 5. The latest Service Pack
for v3.1i is available at: http://support.xilinx.com/support/techsup/sw_updates/

--------------------------------------------------
Previous IP update Requirement
--------------------------------------------------
D_IP2a update is cumulative; therefore, previous IP updates are not required. If you are a
WorkStation user and have already installed 3.1i_ip_update1 (D_IP1) on your system, your
system administrator may need to change the permissions on your current CORE Generator
installation before you install the D_IP2 update. This can be done using the following
command:

chmod -R u+w $XILINX/coregen

-------------------------
Virtex-II Support
-------------------------
New Virtex-II cores have been added to D_IP2. These cores will utilize Virtex-II-specific
fabrics such as Multiplier 18x18 and RAMB16. However, the ability to functionally simulate
and implement Virtex-II designs became available in 3.1i Service Pack 6, which was
released in December, 2000.

-----------------------------------------------------
COREGen "Out of Memory" Error
-----------------------------------------------------
CORE Generator may run out of memory when trying to generate large cores such as
DA FIR and Block Memories. (Xilinx Answer #9244)

----------------------------------------------------------------------------------------------------------
COREGen may error out if invoked from outside the Project Directory
----------------------------------------------------------------------------------------------------------
Error Message: "When generating core_name, your current working directory dir_name should
be the same as your Coregen project proj_dir. "

This note applies to the following cores:

- Sequential and Constant Coefficient Multipliers - part of the Multiplier
(Generator), Version 2.0
- Single Port Block Memory, Version 3.0
- Dual Port Block Memory, Version 3.0

If CORE Generator is invoked from any where other than the Project Directory set in the CORE
Generator GUI, the core generation may fail with the above error message.
(Xilinx Answer #10459)

-----------------------------------------------------------------------------------
Verilog and VHDL Model Delivery and Compile Order
-----------------------------------------------------------------------------------
The HDL behavioral simulation models for the updates are included in the IP update archives
under:

$XILINX/verilog/src/XilinxCoreLib/ (for Verilog) and
$XILINX/vhdl/src/XilinxCoreLib/ (for VHDL)

Compile order information is now documented for each IP release in the respective analyze
order files:

$XILINX/verilog/src/XilinxCoreLib/verilog_analyze_order
$XILINX/vhdl/src/XilinxCoreLib/vhdl_analyze_order

NOTE: In D_IP2, compiling VHDL models for Block RAMs does not require the -93 compliancy
switch as did D_IP1.

-------------------------------------------------
Verilog Model Race Conditions
-------------------------------------------------
Running Verilog behavioral simulation may give race conditions for some cores.
(Xilinx Answer#10461)

--------------------------------------------------------------------------------------------------
Cannot start COREGen from Foundation ISE Project Navigator
--------------------------------------------------------------------------------------------------
After installing Xilinx 3.1i Service Pack 5, new CORE Generator sources cannot be created.
(Xilinx Answer #10434)

--------------------------------------------------------------------------------------------------
Symbol file not generated for Foundation ISE Schematics Tool
--------------------------------------------------------------------------------------------------
The schematic Capture tool that comes with Foundation ISE is also known as ECS. CORE
Generator may fail to generate correct symbol files for ECS Schematic flow.
(Xilinx Answer #9910)

NOTE: There is no work-around for the 12x12 Multiplier and the 8x8 Multiplier. If you are
using ECS Schematics, please use other multipliers that are available for the XC4000 family.

-----------------------------------------------------------------------------------------------------------------------------------------------
Cores instantiated in Foundation ISE Schematics Tool (ECS) fail in simulation and Translate
-----------------------------------------------------------------------------------------------------------------------------------------------
Schematics with instantiated CORE Generator symbols fail in functional simulation and
Translate due to output pins being labeled as input pins. (Xilinx Answer #10451)


IP KNOWN ISSUES

----------------------------------------------------------
Multiplier v2_0 for Virtex and Virtex-II
----------------------------------------------------------
The new Multiplier v2_0 core now merges the ability to generate the following cores into
one module:

- Variable Parallel Multiplier
- Sequential and Serial-Sequential Multiplier
- Fixed and Reloadable Constant Coefficient Multiplier

Multiplier v2_0 supersedes the Variable Parallel Multiplier v2.0 and Dynamic Constant
Coefficient Multiplier v2.0 cores from the previous releases. (Xilinx Answer #10389)

--------------------------------------------------------------
Single- and Dual-Port Block Memory v3_0
--------------------------------------------------------------
The Single- and Dual-Port Block Memory Core Generators for the Virtex and Virtex-II families
have been merged into the new "Block Memory" core v3.0. Please use this new core instead of:

Block Memory Dual Port Virtex-II: v2_0
Block Memory Single Port Virtex-II: v2_0
Dual Port Block Memory : v1_0
Single Port Block Memory: v1_0

(Xilinx Answer #10389)

The .coe file format has changed from previous versions of Block Memory cores. Please see
the data sheet for the new format. (Xilinx Answer #10487)

---------------------------------------------------------------------------
Initializing cores using .coe and .mif files
--------------------------------------------------------------------------
Affected Cores:

-Single and Dual Port Memory
- Distributed Memory
- RAM-based Shift Register

Only .coe files can be used for initializing the above cores. The memory initialization file (.mif)
is no longer accepted by CORE Generator as an input file. However, CORE Generator will
always automatically put out a .mif file for behavioral simulation purposes only.

-------------------------------------------------------------------------------------------------------------------
Dual- and Single-Port Block Memory v3_0 cannot be generated with .coe
-------------------------------------------------------------------------------------------------------------------
When generating Dual- or Single-Port Block Memory v3_0 with the .coe file specified, you
will get the error: "Xilinx CORE Generator An error has occurred". (Xilinx Answer #10549)

-------------------------------------------------------------------------------------
Dual-Port Block Memory Simultaneous Read and Write
-------------------------------------------------------------------------------------
When simultaneous read and write to the same location occurs, the write operation will
always succeed, but the read operation will not be guaranteed. (Xilinx Answer #10462)

-------------------------------------------------------------------
Asynchronous FIFO v3_0 Simulation Issue
-------------------------------------------------------------------
The behavioral simulation and back-annotated simulation do not match when rd_clk and
wr_clk are asynchronous. (Xilinx Answer #10494)

--------------------------------------------------------------
8b/10b Decoder v1_0 for (Virtex Family)
--------------------------------------------------------------
When using Virtex, the user will need to initialize the core with a valid positive or negative
disparity symbol, and the core will output an incorrect symbol disparity (SYM_DISP[1:0])
when SINIT is active. (Xilinx Answer #10475)

------------------------------------------------------------------------------------------------------
Cannot select Sine-Cosine Look-Up Table for XC4000 or Spartan
------------------------------------------------------------------------------------------------------
After installing the D_IP2a update, you may not be able to see the Sine-Cosine Look-Up
Table v_1.0 for generation. (NOTE: v2.1 of this core supports the Virtex and Spartan-II
families only.) (Xilinx Answer #10463)
AR# 10382
Date Created 10/25/2000
Last Updated 08/23/2002
Status Archive
Type General Article