General Description: What can I do if my design is consuming too much memory and hard drive space?
Solution
Many memory issues that deal with large designs have been resolved in an upcoming FPGA Express: Version 3.5.
If you are instantiating a component many times (in the hundreds), then synthesize the component by itself (making sure to deselect Insert I/O) so that you have an EDIF netlist. Then, instantiate the component as a black box in your top level design.