# AR# 10426

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## Description

When should I use an OFFSET constraint in my design?

## Solution

Offsets are used to define the timing relationship between an external clock and its associated data-in or data-out pin. You can use this option to do the following:
• Calculate whether a setup time is violated at a flip-flop whose data and clock inputs are derived from external nets.
• Specify the delay of an external output net derived from the Q output of an internal flip-flop that is clocked from an external device pin.

Using the OFFSET constraint has the following advantages:
• The clock path delay is included for each individual synchronous element.
• It subtracts the clock path delay from the data path delay for inputs, and adds the clock path delay to the data path delay for outputs.

The paths that can be covered are illustrated in Figure 1, and the timing diagrams for the OFFSET IN and OFFSET OUT are shown in Figures 2 and 3, respectively:

OFFSET Example Schematic

OFFSET IN Timing Diagram

OFFSET OUT Timing Diagram
• It includes paths for all synchronous element types (FFS, RAMS, and LATCHES).
• It utilizes a global syntax that allows all inputs or outputs to be constrained by a clock.
• It allows specification of I/O constraints either directly as the setup and clock-to-out required by a device (IN BEFORE and OUT AFTER), or indirectly as the time used by the path external to the device (IN AFTER and OUT BEFORE).

The three basic types of offset specifications are: Global, Net-Specific, and Group.
The OFFSET constraint covers the path between Pad(s)-to-Synchronous and Synchronous-to-Pad(s). Consequently, Xilinx recommends that your design contain at least a Global OFFSET IN and a Global OFFSET OUT. If certain paths must be faster or slower than the global constraints, use the Net-Specific or Group offsets.
For more details on timing constraints, please see the Timing Constraints User Guide:http://www.xilinx.com/support/documentation/sw_manuals/xilinx12_1/ug612.pdf
The different kinds of offsets are described in the following four examples:
Example 1 - OFFSET IN BEFORE:
OFFSET IN BEFORE defines the time available for data to propagate from the pad and setup at the synchronous element (COMP). You can visualize this time as the time differential of data arriving at the edge of the device before the next clock edge arrives at the device. (See Figure 1 and Figure 2.) The following equation defines this relationship:
TDATA + TSU - TCLK TIN_BEFORE
Example 2 - OFFSET IN AFTER:
This constraint describes the time used by the data external to the FPGA. OFFSET subtracts this time from the PERIOD declared for the clock to determine the time available for the data to propagate from the pad and setup at the synchronous element. You can visualize this time as the differential of data arriving at the edge of the device after the current clock edge arrives at the edge of the device. (See Figure 1 and Figure 3.) The following equation defines this relationship:
TDATA + TSU - TCLK TP - TIN_AFTER (TP is the clock period.)
A PERIOD or FREQUENCY is required only for OFFSET OUT constraints with the BEFORE keyword, or OFFSET IN constraints with the AFTER keyword.
Example 3 - OFFSET OUT AFTER:
This constraint defines the time available for the data to propagate from the synchronous element to the pad. You can visualize this time as the differential of data leaving the edge of the device after the current clock edge arrives at the edge of the device. (See Figure 1 and Figure 3.) The following equation defines this relationship:
TQ + TCO + TCLK TOUT_AFTER
Verification involves ensuring that the maximum delay along the reference path (CLK_SYS to COMP) and the maximum delay along the data path (COMP to Q_OUT) do not exceed the specified offset.
Example 4 - OFFSET OUT BEFORE:
This constraint defines the time used by the data external to the FPGA. OFFSET subtracts this time from the clock PERIOD to determine the time available for the data to propagate from the synchronous element to the pad. You can visualize this time as the differential of data leaving the edge of the device before the next clock edge arrives at the edge of the device. (See Figure 1 and Figure 3.) The following equation defines this relationship:
TQ + TCO + TCLK TP - TOUT_BEFORE
Verification involves ensuring that the maximum delay along the reference path (CLK_SYS to COMP) and the maximum delay along the data path (COMP to Q_OUT) do not exceed the clock period minus the specified offset.
As in Example 2, a PERIOD or FREQUENCY constraint is required only for offset OUT constraints with the BEFORE keyword, or offset IN with the AFTER keyword.
AR# 10426
Date 02/06/2013
Status Active
Type General Article
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