The "core" cells will not present a problem, with the possible exception of the BUFGMUX. Because FPGA Express will not recognize the BUFGMUX as a valid primitive, FPGA Express will treat it as a black box. This will cause FPGA Express to insert an IBUF in front of a BUFGMUX.
You should instantiate the IBUFG preceding the two clock inputs of the BUFGMUX; FPGA Express recognizes the IBUFG as a valid I/O buffer, causing it to not insert I/O buffers before the IBUFGs.