This example infers the RAM16X1D_1 primitive, which is not supported for XC4K and Spartan/XL families.
The work-around is to put a syn_keep on the inverted clock net so that the inverter is not absorbed into the RAM16X1D:
wire clk_n /* synthesis syn_keep = 1 */;
2
The following example illustrates coding that could cause the incorrect RAM16X1D_1 inference:
library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all;
entity test is port (din : in std_logic_vector (3 downto 0); waddr : in std_logic_vector (3 downto 0); raddr : in std_logic_vector (3 downto 0); clk : in std_logic; we : in std_logic; dout : out std_logic_vector (3 downto 0)); end entity;
architecture test_arch of test is
type mem_type is array (15 downto 0) of std_logic_vector (3 downto 0); signal mem : mem_type; signal clk_n : std_logic;
begin
clk_n <= NOT(clk);
process(clk) begin if clk_n'event and clk_n = '1' then if (we = '1') then mem(conv_integer(waddr)) <= din; end if; end if; end process;
process(raddr) begin dout <= mem(conv_integer(raddr)); end process;
end test_arch;
This example infers the RAM16X1D_1 primitive, which is not supported for XC4K and Spartan/XL families.
The work-around is to put a syn_keep on the inverted clock net so that the inverter is not absorbed into the RAM16X1D:
library synplify; use synplify.attributes.all; : : attribute syn_keep of clk_n : signal is true;
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AR# 10460
Date
03/05/2006
Status
Archive
Type
General Article
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