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  3. AR# 10487: 3.1i COREGEN - Xilinx CORE Generator: "An Error has occurred.... Invalid parameter..."

AR# 10487

3.1i COREGEN - Xilinx CORE Generator: "An Error has occurred.... Invalid parameter..."

Description

Keywords: single, dual, port, block, memory, coe, format, coregen,
d_ip2, 3.1i, ip, update, xilinx, core, generator, invalid, parameter

Urgency: Standard

General Description:
Generating a Single or Dual Port Block Memory v3_0, or a Distributed Memory
or RAM-based Shift Register causes the error:

"Xilinx CORE Generator - An Error has occurred....
-----------------------------------------------------------------------
ERROR: Invalid parameter xxxx
ERROR: Did not read Coe File /home/project/dpbram.coe
ERROR: File not found
ERROR: Customization parameter rule checks failed. Terminating core elaboration:
Invalid Coe File name"

Solution

The new Single and Dual Port Block Memory (v3_0) delivered in
3.1i_ip_update2 has a new .coe file format. Old .coe files that
were used in v1_0 or v2_0 of the Block Memory cores will
no longer work. Dist Memory and RAM-based shift register also have
the new .coe format.

Refer to the Block Memory v3_0 datasheet for the correct example.
The only acceptable parameters are:

memory_initialization_radix
memory_initialization_vector

If you have any other parameters in your .coe file, you must remove
them from that .coe file. Commenting the lines out with "#" will not work.

NOTE: The example .coe files in

C:\Xilinx\coregen\data\v_dpbram.coe
C:\Xilinx\coregen\data\v_spbram.coe

will no longer work for v3_0 of the Block Memories.

However, they will still work with the v1_0 and v2_0 of the
Block Memories.
AR# 10487
Date 08/23/2002
Status Archive
Type General Article