Keywords: single, dual, port, block, memory, coe, format, coregen, d_ip2, 3.1i, ip, update, xilinx, core, generator, invalid, parameter
Urgency: Standard
General Description: Generating a Single or Dual Port Block Memory v3_0, or a Distributed Memory or RAM-based Shift Register causes the error:
"Xilinx CORE Generator - An Error has occurred.... ----------------------------------------------------------------------- ERROR: Invalid parameter xxxx ERROR: Did not read Coe File /home/project/dpbram.coe ERROR: File not found ERROR: Customization parameter rule checks failed. Terminating core elaboration: Invalid Coe File name"
Solution
The new Single and Dual Port Block Memory (v3_0) delivered in 3.1i_ip_update2 has a new .coe file format. Old .coe files that were used in v1_0 or v2_0 of the Block Memory cores will no longer work. Dist Memory and RAM-based shift register also have the new .coe format.
Refer to the Block Memory v3_0 datasheet for the correct example. The only acceptable parameters are: