AR# 10495: 3.4 FPGA Express - FPGA Express Constraints Editor does not display top-level clock
3.4 FPGA Express - FPGA Express Constraints Editor does not display top-level clock
Keywords: FPGA, Express, 3.4, constraints
General Description: When a design has a clock input going to multiple instantiated modules, the top-level design is also using the clock in a process/always statement; the top- level clock may not appear in the Synthesis Constraints editor in FPGA Express 3.4 (The clock that does appear in the Synthesis Constraints editor is a lower- level modules clock.)
This is fixed in FPGA Express 3.5. In the 3.5 version, the top-level clock is referenced in the Synthesis Constraints editor.