UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!
Page Bookmarked
  1. Xilinx - All Programmable
  2. Support
  3. AR# 105: Initializing Mentor QuickSim simulation: Net names for the global reset signal

AR# 105

Initializing Mentor QuickSim simulation: Net names for the global reset signal

Description

Keywords: initialize, QuickSim, simulation, global

Urgency: Standard

General Description:

At the start of simulation in Quicksim, the global-reset net must be pulsed
to initialize all flip-flops in the design. What is the name of this net?

Solution


Here is a list of the different signal names used for the global-reset net:

XC2000: //globalresetb (active Low)
XC3000/A/L: //globalresetb (active Low)
XC4000/E/X: //globalsetreset (active High)
Virtex: //globalsetreset (active High)
XC5200: //globalreset (active High)
XC7000: //prld (active High)
XC9500 //prld (active High Functional simulation)
XC9500 /prld (active High for Timing simulation)

For example, in an XC4000 design:

force //globalsetreset 1 0
force //globalsetreset 0 50

The length of the global-reset pulse should be at least the specified
minimum pulse width for an asynchronous set or reset line, as given in the
data book. (This parameter is called Tmrw for FPGAs and Twmr for EPLDs.)
AR# 105
Date 09/30/2008
Status Archive
Type General Article