UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 1050

Designing with the XC9500 family in Mentor (XACT 5.2.x)

Description

Is there a way to design and simulate XC9500 designs in Mentor with XACT
5.2.x?

Solution

This application brief shows how to use Mentor software tools to design
with XC9500 CPLDs.

SYSTEM SETUP
------------
The following software is required:

XACT-CPLD (DS560) XC9500 core tools
Mentor Interface (DS344) Includes XC7000 libraries

You also need to obtain the following patch from the Xilinx FTP site:

men9k.tar.Z Mentor interface patch for XC9500

You may obtain this patch from:

http://www.xilinx.com/txpatches/pub/swhelp/mentor/men9k.tar.Z

The XC9500 software patch should be installed in a separate directory from
any other Xilinx production software. When designing with XC9500 devices,
this directory should appear in the path statement and XACT environment
variable before any other Xilinx software. For example, if you installed
the XC9500 patch in /tools/xact9000, you would need to set:

set path = ( /tools/xact9000/bin/sparc $path )
setenv XACT /tools/xact9500:$XACT

If you are on an HP700, the path setting would instead be:

set path = ( /tools/xact9000/bin/hppa $path )

Remember to remove the XACT9000 directories from the path and XACT
variables when designing with XC7000 CPLDs or Xilinx FPGAs.

DESIGN FLOW
-----------
The design flow relies on the XC7000 libraries for design capture and
simulation. It uses modified versions of the XEPLD and XEPLDsim commands
to interface between the two technologies.

To implement a design for an XC9500 device:

1. Prepare a Mentor schematic using the XC7000 library provided in the
Xilinx-Mentor Interface (DS344), or synthesize an EDDM model from
Autologic using the XC7K library supplied by Mentor. (For information
on obtaining the Autologic library, see Solution 608, "How to obtain the
latest version of the Autologic libraries for Xilinx.") Avoid using
arithmetic symbols (e.g., adders and accumulators), comparators such as
COMPM4 and COMPM8, input latches, and the BUFCE input-register clock
enable, since these symbols use XC7000-specific resources. (Autologic
does not use any of these.)

2. Save the schematic, but DO NOT use Men2XNF8 or XEMake to process the
design.

3. In a Unix command window, execute the following comment while in the
project directory:

xepld <design>

where <design> is the name of the top-level schematic or EDDM component.
The XEPLD command reads the Mentor schematic of EDDM file, translates it
to an XNF netlist and implements the design.

To get a list of all the available command-line options in this program,
type:

xepld -help

You may also look at the XEPLD Schematic Design Guide, Appendix D,
"Design Implementation and Simulation."

The XC9500 implementation software produces the following output files:

<design>.rpt Fitter report (including pinout)
<design>.tim Static timing report
<design>.prg MCS-86 (Intel hex) programming file
<design>_tim.xnf Timing simulation netlist

4. To perform timing simulation on the completed design, first execute the
following while in the project directory:

xepldsim -mentor <design>

This reads the <design>_tim.xnf file and translates it to a new Mentor
component named <design>_tim. To simulate this model:

quicksim <design>_tim

A complete description of the XEPLDsim options is contained in the XEPLD
Schematic Design Guide, Appendix D, "Design Implementation and
Simulation."
AR# 1050
Date Created 06/10/1996
Last Updated 05/19/1999
Status Archive
Type General Article