We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

Page Bookmarked

AR# 10535

4.2i Foundation - The reset signal will not simulate in functional simulation if the VHDL is asynchronous


Keywords: asynchronous, reset, functional, simulation, VHDL

Urgency: Standard

General Description:
When I code an asynchronous flip-flop in VHDL, the reset signal is ignored in pre-synthesis simulation.


Generally, this problem is due to the use of the "GSR" startup block--the synthesis tool simply hooks the asynchronous reset signal to the GSR pin of the startup block and leaves the CLR pin of the inferred FFs unconnected. This will work for implementation, but it does not allow the asynchronous reset to be functionally simulated.

The simplest way to work around this problem is to perform a checkpoint simulation of the NDG file.

Another way to avoid this issue is to create a schematic macro of the VHDL code. When this macro is tested under functional simulation, the reset will function as predicted.
AR# 10535
Date 08/11/2003
Status Archive
Type General Article