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AR# 10547

3.1i CORE Generator - 8b/10b encoder and decoder simulation error - "Instantiation of 'encoder_8b10b_v1_base' failed (design unit not found)."


Keywords: CORE Generator, Coregen, D_IP2, IP update, encoder, decoder, b, 10b,
simulation error, Verilog

Urgency: Standard

General Description:
When performing a behavioral simulation of the encoder in MTI-Verilog, I encounter the
following error:

"ERROR- Instantiation of 'encode_8b10b_v1_base' failed (design unit not found)."

A similar error appears for the decoder.



This problem occurs because the .veo file is missing a library reference to the
encode_8b10b_v1_base.v file.

To solve this problem, add the following line to your testbench or to your source code:
`include "XilinxCoreLib/encode_8b10b_v1_base.v"

For example, your library inclusion would look like this:

//----------- Begin Cut here for LIBRARY inclusion --------// LIB_TAG

// synopsys translate_off
`include "XilinxCoreLib/encode_8b10b_v1_0.v"
`include "XilinxCoreLib/encode_8b10b_v1_base.v" //add this line
// synopsys translate_on

// LIB_TAG_END ------- End LIBRARY inclusion --------------


This problem is scheduled to be fixed in 3.1i IP Update # 3, due out in March, 2001.

AR# 10547
Date 08/23/2002
Status Archive
Type General Article