In the Virtex-E IBIS file, there are two separate models for LVDS: LVDS_TSF and LVDS_MIX. What is the difference between these models?
All IBIS models provide three columns of data: Min, Typ, and Max. These correspond to the PVT (Process, Voltage, Temperature) conditions that were simulated within HSPICE in order to generate the models. Typically, Min = low voltage, high temperature, and slow process. Max = high voltage, low temperature, and fast process.
The difference between LVDS_TSF and LVDS_MIX models is the PVT conditions used to create them. The LVDS_TSF model was derived with the PVT conditions outlined above, while the LVDS_MIX was derived with a slightly different combination of PVT conditions.
Both LVDS_TSF and LVDS_MIX models should be simulated in order to verify signal integrity. Note that this approach is unique to Virtex-E.
IBIS models of all Xilinx devices can be found at: