AR# 10574: 3.1i XST - The VHDL LOC attribute is ignored.
AR# 10574
3.1i XST - The VHDL LOC attribute is ignored.
Description
Keywords: XST, VHDL, LOC, attributes, constraints
Urgency: Standard
General Description: The LOC attribute is not passed on to the NCF file when it is placed inside the architecture section of the VHDL code.
Solution
To correct this problem, place the LOC constraint instantiations and assignments inside the entity section of the design.
For example: library ieee; use ieee.std_logic_1164.all;
entity test_ff is port (d : in std_logic; clk : in std_logic; q : out std_logic); attribute LOC : string; attribute LOC of d : signal is "D8"; --where D8 is the pin name end entity;
architecture arch_ff of test_ff is
begin
process (clk) begin if clk'event and clk = '1' then q<=d; end if;