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  1. Xilinx - All Programmable
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  3. AR# 10585: 3.1i CPLD Hprep6 - XC9500 device operation does not match simulation

AR# 10585

3.1i CPLD Hprep6 - XC9500 device operation does not match simulation

Description

Keywords: 9500, Jedec

Urgency: Hot

General Description:
For XC9500 (5V) devices: In Jedec generation, signal outputs do not match
the timing simulation. (This only affects XC9500 5-volt devices.)

Solution

This is fixed in the latest 3.1i Service Pack available at:
http://support.xilinx.com/support/techsup/sw_updates.
The first service pack containing the fix is 3.1i Service Pack 6.
AR# 10585
Date 08/23/2002
Status Archive
Type General Article