AR# 10598: 3.5 FPGA Express - What's New in Express 3.5?
3.5 FPGA Express - What's New in Express 3.5?
Keywords: FPGA Express 3.5
General Description: What are the new features in FPGA Express 3.5 (delivered with Xilinx Service Pack 6)?
The following features were introduced in version 3.5 of FPGA Express:
Fast Synthesis Option
Version 3.5 of FPGA Express introduces the Fast Synthesis option. Selecting "Fast effort" in the "Create Implementation" dialog box reduces compilation time significantly while maintaining results of competitive quality.
Version 3.5 of FPGA Express introduces a DesignWizard to guide you through the entire synthesis process in two easy steps. When you start FPGA Express, the DesignWizard appears automatically. The first screen (FPGA Project dialog box) allows you to create a new project or open an existing one.
You also have the option to disable DesignWizard on subsequent starts of the tool.
To start DesignWizard manually, select "DesignWizard" from the File menu.
New HDL Compiler for Verilog
Version 3.5 of FPGA Express introduces a new HDL Compiler for Verilog. One feature of this compiler allows you to implement "fastest and smallest" as well as "safest" Finite State Machines (FSMs) in Verilog in the same way currently possible for VHDL designs.
To enable the new HDL Compiler, select "New HDL Compiler - Presto for Verilog Synthesis" in Synthesis > Options > Project. Checking the New HDL Compiler box makes the "fastest and smallest" as well as "safest" switches for FSM synthesis available to Verilog FSMs.
The corresponding shell variable for enabling the new HDL Compiler for Verilog is:
proj_compiler_type = presto
(NOTE: You must "Force Update" your design source files for the change to the new HDL Compiler in order for this to take effect.)
Version 3.5 of FPGA Express adds ROM inference support for the following architectures:
Refer to the application note "Inferring Read Only Memory in FPGA Compiler II and FPGA Express" on Synopsys' web site for more information.
ASCII Constraint File
Version 3.5 of FPGA Express supports the exporting and importing of ASCII constraint files.
Constraints can be exported from constraint tables to an ASCII file. You can edit the file and later import it to the project.
NOTE: The ASCII constraint file can only be imported to the same implementation from which it was exported.
Refer to "Getting Started" or online help for more information.
Multiple NCF files for Block-Level Incremental Synthesis
Version 3.5 of FPGA Express supports multiple NCF files for Block-Level Incremental Synthesis.
If Export Timing Specifications is selected in the Export Netlist dialog box, the tool generates a .ncf file for each block to pass timing constraints to the place and route tools. The names of the .ncf files are the same as the module/entity/netlist name of the respective block roots.
Refer to the application note "Using Block-Level Incremental Synthesis in FPGA Compiler II and FPGA Express" on Synopsys' web site for more information.
New Architectures Supported
The following architectures were added in version 3.5 of FPGA Express:
Xilinx Virtex-II Xilinx Virtex-EM
Enhancements to Architecture Support
Version 3.5 of FPGA Express includes the following architecture-specific enhancements to synthesis and optimization:
Improved Support for Multiplexors
Version 3.5 of FPGA Express relaxes the requirements for MUX_OP inference. Refer to the application note "Inferring Multiplexors in FPGA Compiler II and FPGA Express" on Synopsys' web site for more information.
Improved Constant Comparator Support for Xilinx Virtex and Virtex-II
Version 3.5 of FPGA Express takes advantage of LUTs for constant comparator of fifteen to eighteen bits to reduce area and delay. For constant comparators larger than eighteen bits, CYMUXes are used in addition to LUTs.
LVDS I/O Support for Xilinx Virtex-E
Improved TimeTracker accuracy for Xilinx Virtex and its derivatives
New Error and Warning Viewer
Version 3.5 of FPGA Express categorizes error and warning messages in the Output window. To view individual messages, click the "+" sign next to the message group icon to expand the list.
Enhancements to Graphical User Interface
Version 3.5 of FPGA Express supports the display of buses in the Schematic Viewer.
Man Pages in HTML Format
Version 3.5 of FPGA Express added the man pages in HTML format.