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AR# 10611

3.1i SP6 - 3.1i Service Pack 6 update

Description

Keywords: Service, Pack, 3.1i, update,

Urgency: Standard

General Description:
This answer contains a complete list of all changes included in the
M3.1i Service Pack 6 Update.

This is the sixth service pack since the release of 3.1i. This service pack also
contains some quarterly updates, and for this reason may also be referred to
as version 3.3i.

Solution

The Service Pack Update Page is located at:
http://support.xilinx.com/support/techsup/sw_updates/
The following issues are addressed by the 3.1i Service Pack 6 Update:

INSTALL

(Xilinx Answer #9672): 3.1i Service Pack Install - Canceling the
Service Pack Install gives message - Install Completed Successfully

NGDBUILD

(Xilinx Answer #9536): 3.1i Virtex-E Map - Crash after "Running
Directed Packing..." due to incorrect MUXF5 trimming.

(Xilinx Answer #9573): 3.1i NGDBuild - Fatal-Error:Utilities:utilblist.c:234:1.4
MAX ELEMENT COUNT EXCEEDED.

(Xilinx Answer #9573): 3.1i NGDBuild - "FATAL_ERROR:Utilities:UtilBlist.c:234:1.4
Maximum element count exceeded..."

(Xilinx Answer #10223): 3.1i NGDBuild - XML Parser environment is incorrectly set
up, preventing it from finding its text transcoding files.

MAP

(Xilinx Answer #10213): 3.1i MAP - FATAL_ERROR: MapHelpers:
mhcconstimp.c:162:1.7.20.1 - resolveSiteType() ...

(Xilinx Answer #9536): 3.1i Virtex-E MAP - Crash after "Running
Directed Packing..." due to incorrect MUXF5 trimming.

(Xilinx Answer #9534): 3.1i Virtex-E MAP - FATAL_ERROR:
Pack:pksvrsliceusg.c:508:1.20.10.1 Never found the LUT address
signal

(Xilinx Answer #9723): 3.1i Virtex MAP - RPM macro's carry chain
alignment disrupted by map trimming.

(Xilinx Answer #9053): 3.1i Virtex MAP - Problems with
implementation and back annotation of FDCP with INIT=R.

(Xilinx Answer #9591): 3.1i Virtex MAP - Core dump (bus error)
during modular design assembly phase.

(Xilinx Answer #9344): 3.1i Virtex MAP - Some eligible registers
are not being packed into IOBs.

(Xilinx Answer #9077): 3.1i Virtex MAP - ERROR:DesignRules:368 -
Netcheck: Sourceless. Net $3I2/..... has no source.

(Xilinx Answer #10027): 3.1i Virtex MAP - ERROR:Pack:679 - Unable
to obey design constraints ...

(Xilinx Answer #10028): 3.1i Virtex MAP - ERROR:Pack:679 - Unable
to obey design constraints ...

(Xilinx Answer #10254): 3.1i Virtex MAP - A bad NGM file is
produced by MAP, affecting simulation results.

(Xilinx Answer #9973): 3.1i Virtex MAP - ERROR:Pack:679 - Unable to
obey design constraints.

(Xilinx Answer #10026): 3.1i Virtex MAP - RAM/SRL16E packed with
latch results in bad clock inversion.

(Xilinx Answer #10575): 3.1i Virtex MAP - Combined BLKRAM and slice-based area-
groups are not translated correctly to PCF.

(Xilinx Answer #9940): 3.1i Virtex-E MAP - MAP runs out of memory while loading
NGD under Windows2000.

PAR

(Xilinx Answer #10392): 3.1i Virtex PAR -
FATAL_ERROR:Route:basrtsanity.c:168:1.7.28.1 - Process will
terminate.

(Xilinx Answer #10284): 3.1i Virtex PAR - FATAL_ERROR: Route:
basrtalg.c:148:1.8.2.2 - deposit: vccgnd_splitnet....

(Xilinx Answer #10312): 3.1i Virtex PAR - Dr. Watson Error
"0xC0000005 0x0693628F7" when implementing ChipScope core.

(Xilinx Answer #9732): 3.1i Virtex PAR - Problem with data file
causes v300cb228 design to get internal error.

(Xilinx Answer #9729): 3.1i Virtex PAR - Router crash during
PWR/GND routing.

(Xilinx Answer #9519): 3.1i Virtex-E PAR -
INTERNAL_ERROR:Place:baspltaskmincut.c:453:1.12 - Matcher did not
find a solution.

(Xilinx Answer #9589): 3.1i Virtex PAR - Guided PAR fails with
ERROR:Portability:3 - This Xilinx application has run out of memory.

(Xilinx Answer #9588): 3.1i Virtex PAR - Range constraint expansion
in Modular Design uses too much memory.

(Xilinx Answer #9359): 3.1i Virtex PAR- Illegal pin swaps may occur
on address pins of SRL16E.

(Xilinx Answer #9587): 3.1i XC4000XLA PAR - Pad report does not
report all the Vcc pins for XC044XLA-HQ304.

(Xilinx Answer #9345): 3.1i Virtex PAR - Placer crashes on designs
with RPM macros containing Block RAM.

(Xilinx Answer #9250): 3.1i Virtex-E PAR - PAR runs out of memory
on a design with offset in constraints.

(Xilinx Answer #8937): 3.1i Virtex PAR - PAR hangs during PWR/GND
routing.

(Xilinx Answer #9372): 3.1i XC5200 PAR - MPPR PAR runs crash on 2nd
pass for 5200 designs.

(Xilinx Answer #9725): 3.1i Virtex-E PAR - PAR takes a long time
during the "Generate PAR statistics" phase.

(Xilinx Answer #9484): 3.1i PAR - Guided PAR fails with error :
Place:489 The clock group consisting of the following components ...

(Xilinx Answer #10049): 3.1i Virtex-E PAR - The router doesn't
always use a long line when one is available.

(Xilinx Answer #8992): 3.1i XFLOW - ERROR:Trace:19 - Unable to
access design file after Control-C (Ctrl-C) is used to interrupt PAR.

(Xilinx Answer #9437): 3.1i Virtex-E PAR - Placer crashes while
handling range constraints on IOBs.

(Xilinx Answer #9873): 3.1i Virtex-E PAR - Placer rejects placement
of slices containing F5/F6 muxes.

(Xilinx Answer #10256): 3.1i Virtex-E PAR - Problem with DLLIOB
SelectIO input and placement.

(Xilinx Answer #10255): 3.1i Virtex PAR - Long PWR/GND runtimes
have been seen for Virtex designs.

(Xilinx Answer #10116): 3.1i PAR - PAR runs out of memory.

(Xilinx Answer #10561): 3.1i Virtex-E PAR - Placer rejects placement of slices
containing F5/F6 MUX.

(Xilinx Answer #10566): 3.1i Virtex PAR - Placer places two signals on one SIGPIN.

TIMING

(Xilinx Answer #3513): 3.1i Timing Analyzer - GDI resources taken
up when scrolling on a report.

(Xilinx Answer #9297): 3.1i Timing - Multi-Cycle (FROM:TO) path
constraint is getting picked up by PERIOD constraint.

(Xilinx Answer #9619): 3.1i FPGA Editor - Core dumps when
specifying IOBs to drive '0'.

(Xilinx Answer #10264): 3.1i Timing Analyzer : Custom analysis brings up empty
report for CPLDs.

HARDWARE DEBUGGER

(Xilinx Answer #9630): 3.1i Hardware Debugger - Internal DCE
Threads problem while running on HP platform.

BITGEN

(Xilinx Answer #10401): 3.1i BitGen - TDO2 programmable inverter
equations are wrong (TDO2 is wrong polarity).

(Xilinx Answer #10402): 3.1i BitGen - IOB FF worked using 2.1i
BitGen but stuck in reset using 3.1i

(Xilinx Answer #9705): 3.1i BitGen - BitGen will create a debug
bitstream with the option DebugBitstream:No.

(Xilinx Answer #9707): 3.1i BitGen - Feedback 2x memory cell is not
set correctly when using DLLIOB for feedback.

(Xilinx Answer #9706): 3.1i BitGen - LVPECL inputs on top edge of
Virtex-E devices are not configured properly.

(Xilinx Answer #9431): 3.1i BitGen - ERROR: 145 - Pin ... is a
persistent pin, but a component ..."

(Xilinx Answer #9429): 3.1i Virtex-E BitGen - Greater than a 0.3 ns
difference seen between the input clock of a DLL and the feedback
path.

(Xilinx Answer #9922): 3.1i BitGen - I/O's are not 5V tolerant for
Virtex architectures (Vcco rail is rising above 3.3V).

DESIGN MANAGER

(Xilinx Answer #9606): 3.1i Design Manager - Post Layout Timing
Report should not be automatically generated after executing MPPR.

JTAG PROGRAMMER

(Xilinx Answer #9790): 3.1i JTAG Programmer - HP-UX crashes or does
not connect with the XChecker cable

(Xilinx Answer #9646): 3.1i JTAG Programmer - When write protect is
selected, the checksum will mismatch.

(Xilinx Answer #9791): 3.1i Virtex JTAG Programmer - SVF status
check on DONE pin fails.

(Xilinx Answer #9647): 3.1i JTAG Programmer - Dr. Watson error
while trying to generate SVF program device.

(Xilinx Answer #9645): 3.1i XC1800 JTAG Programmer - XC1804 remains
in ISP mode after operation has finished.

(Xilinx Answer #9644): 3.1i XC9500 JTAG Programmer - On programming
failure, Xilinx software does not erase the CPLD.

(Xilinx Answer #8224): 3.1i XC18V00 JTAG Programmer - JTAG
Programmer 3.1i does not support XC18V00 SVF generation.

(Xilinx Answer #10405): 3.1i XC18V00 JTAG Programmer - added
NORMRST between program and verify for 18V01, 18V512 18V256

(Xilinx Answer #10252): 3.1i XC18v00 JTAG Programmer - "Verify"
option disabled in program options dialog.

(Xilinx Answer #10059): 3.1 JTAG Programmer - MultiLINX cable does
not consistently program 18v04 for Parallel Mode.

(Xilinx Answer #10253): 3.1i XC18v00 JTAG Programmer - SVF for Get
USERCODE fails with wrong value.

(Xilinx Answer #9862): 3.1i XC18v00 JTAG Programmer - SVF verify
unsuccessful.

(Xilinx Answer #10005): 3.1i XC18v00 JTAG Programmer - missing the
XC18V256 VQ44 part.

(Xilinx Answer #10018): 3.1i XC1800 JTAG Programmer - PROM verify
voltage margin raised.

(Xilinx Answer #9452): 3.1i JTAG Programmer - ERROR: JTag - Illegal character ?
(/37777777637) at line 633 in BSDL description.

(Xilinx Answer #10585): 3.1i CPLD Hprep6 - XC9500 device operation does not match
simulation.

CPLD

(Xilinx Answer #9731): 3.1i CPLD TAEngine - 95288xl-7 speed grade
displays -10 timing values.

(Xilinx Answer #9004): 3.1i CPLD 9500XV Hitop - Only LVTTL
bi-directional signals allowed.

(Xilinx Answer #4100): 3.1i XC9500 Family Hitop - PROHIBIT property
does not exclude pins from "Programmable Ground Pins" option.

(Xilinx Answer #9658): 3.1i CPLD TAEngine - Fails to expand
wildcards [*] when processing timing constraints.

(Xilinx Answer #9824): 3.1i CPLD HPrep6 - When will JEDEC support
be enabled for the XC9500XV Family?

FLOORPLANNER

(Xilinx Answer #9934): 3.1i Floorplanner - Pin LOC gets changed
from the Placement window to the Floorplan window.

(Xilinx Answer #9171): 3.1i Floorplanner - Constraints are not
being implemented correctly.

(Xilinx Answer #6240): 3.1i Floorplanner - Write AG constraints in
UCF to *not* include lower-level instances.

(Xilinx Answer #8136): 3.1i Virtex-E Floorplanner - Secondary DLL
does not appear in the Floorplanner.

(Xilinx Answer #2740): 3.1i Floorplanner - Pin constraints in ucf
file show up incorrectly in the Floorplanner.

(Xilinx Answer #9033): 3.1i Floorplanner - Error Portability 3:
application has run out of memory or Segmentation Fault.

(Xilinx Answer #10014): 3.1i Floorplanner - Crashes/Core Dumps when
loading design

CABLES

(Xilinx Answer #8777): 3.1i MultiLINX Cable - Issues with Windows98 SE,
Windows2000 and USB.

FPGA EDITOR

(Xilinx Answer #9357): 3.1i Virtex FPGA Editor - Adding a pin to
GLOBAL_LOGIC signal leads to crash.

(Xilinx Answer #8697): 3.1i FPGA Editor - Trace Summary selects the
wrong constraint.

(Xilinx Answer #10015): 3.1i FPGA Editor - Crashes when saving NCD
after modifying design.

(Xilinx Answer #10015): 3.1i FPGA Editor - Crashes when saving NCD
after modifying design.

(Xilinx Answer #9975): 3.1i FPGA Editor - Crashes when trying to
implement the ILA features.

PACKAGE FILES

(Xilinx Answer #10393): 3.1i Virtex-E Package Files - The BG560
package is now available for XCV400E and XCV600E.

(Xilinx Answer #3149): 3.1i Package Files - Spartan XCS10 TQ144
does not have TMS pin bonded.

(Xilinx Answer #10030): 3.1i XC4000XL/XC4000XLA Package Files -
Missing pins result in incomplete .pad file from PAR.

(Xilinx Answer #10031): 3.1i XC4000XLA Package Files - The
XC4085XLA BG352 package has bad pinout.

(Xilinx Answer #10032): 3.1i Virtex Package Files - XV150 FG456
missing VCC pin J7 leading to incomplete .pad file.

(Xilinx Answer #10037): 3.1i Spartan-II Package Files - x2s15 TQ144
package missing N.C. pins leading to incomplete .pad file.

(Xilinx Answer #10050): 3.1i Spartan Package Files - Packages are
missing some no connect pins, affecting .pad report.

(Xilinx Answer #10051): 3.1i XC4000E Package Files - Several
package files are missing pins, affecting the .pad file.

(Xilinx Answer #10052): 3.1i Virtex Package Files - The Virtex
CB228 package files are missing pins, affecting the .pad report.

(Xilinx Answer #10259): 3.1i Virtex-II Package Files - New
Virtex-II package files are included in 3.1i Service Pack 4.

SPEED FILES

(Xilinx Answer #10054): 3.1i Virtex-E Speed Files - ERROR:Trace:12
- Invalid speed "min" specified on command line.

(Xilinx Answer #10055): 3.1i Spartan-II Speed Files - PRELIMINARY
-5 files are available for Spartan-II

(Xilinx Answer #10258): 3.1i Speed Files - Speed File changes for
3.2i SP4.

(Xilinx Answer #10582): 3.1i Virtex-E Speed Files - A speed modeling problem which
affected the clock skew has been fixed.

(Xilinx Answer #10581): 3.1i Virtex-E Speed Files - New speed models have been
added for Virtex-E global clocks.

(Xilinx Answer #10359): 3.1i Speed Files - WARNING: Timing:180 -Pulse- width error
at comp "maindll".

(Xilinx Answer #10395): 3.1i Spartan-II Speed Files - ADVANCED MINs for Spartan-II
are now available.

(Xilinx Answer #9327): 3.1i Virtex-E Speed Files - LVDS input feeding DLL with internal
feedback needs additional 0.5 ns delay

PROJECT NAVIGATOR

(Xilinx Answer #10228): 3.1i Foundation ISE - Online Help Missing
for Waveform Viewer in Foundation ISE 3.1.

(Xilinx Answer #9388): 3.1i Foundation ISE - Double Clicking on XCO
file from within Project Navigator fails.

(Xilinx Answer #9721): 3.1i Foundation ISE- MTI Error: Cannot open
macro file: top.vfd' - this file is not created.

(Xilinx Answer #9722): 3.1i Foundation ISE - "Insert I/O Pads" not
working with FPGA Express flow.

(Xilinx Answer #10225): 3.1i Foundation ISE - Project Navigator
does not support ABEL test vector (ABV) files.

(Xilinx Answer #10226): 3.1i Foundation ISE - Addition of a VHDL or
Verilog source causes Project Navigator to hang.

(Xilinx Answer #10227): 3.1i Foundation ISE - Running MPPR from
Foundation ISE causes the PC to hang.

(Xilinx Answer #10228): 3.1i Foundation ISE - Online Help Missing
for Waveform Viewer in Foundation ISE.

(Xilinx Answer #10204): 3.1i Foundation - Question marks appear on
Design Entry and Synthesis toolbox after implementation.

PROM FILE FORMATTER

(Xilinx Answer #9708): 3.1i PROM File Formatter - Spartan-II PROMs
not selectable (17S50XL, 17S100XL, 17S150XL, 17S200XL)

(Xilinx Answer #10034): 3.1i PROM File Formatter - 18v00 parts
should be listed in PROM device list.

(Xilinx Answer #9569): 3.1i PROM File Formatter - 17S05XL is listed
with the wrong size.

SCHEMATIC CAPTURE

(Xilinx Answer #10279):3.1i Foundation - Exporting design netlist
causes GPF in module conv_acs.dll

ECS

(Xilinx Answer #10280): 3.1i Foundation ISE - ECS property on
CLKDLL, CLKDLLE, CLKDLLHF and DCM does not work

CHIP VIEWER

(Xilinx Answer #9382): 3.1i CPLD ChipViewer - ChipViewer fails to
start (Out of environment space).

(Xilinx Answer #9901): 3.1i ChipViewer - Timing analyzer results
are not being shown.

(Xilinx Answer #10587): 3.1i CPLD ChipViewer - Hangs on "Resizing Layout" when
targeting XC95288XL-6 device.

NCDesign

(Xilinx Answer #10156): 3.1i Virtex-E NCDesign - Software will not
support IBUFG_LVDS inputs for XCV405E.

NGD2VER

(Xilinx Answer #10302): 3.1i Virtex-E NGD2VER - time_sim.vhd file
contains generic FACTORY_JF for X_CLKDLL2 module which is not in
Simprims model.

UNISIM

(Xilinx Answer #10578): 3.1i UNISIMS - CLKDLLHF does not activate LOCK without a
reset pulse in simulation. (Verilog)

(Xilinx Answer #10577): 3.1i Mentor SIMPRIMS - INIT property is missing on X_LUT4,
X_LUT3 and X_LUT2 symbols.

(Xilinx Answer #9215): 3.1i Virtex-E UNISIMS - CLKDLL doesn't lock in simulation if
Clock remains low for one period upon start of simulation.

(Xilinx Answer #10469): 3.1i UNISIMS and SIMPRIMS - Output of Dual Port Block
RAMs do not reset when RST is asserted and there is a collision.

FPGA Express

(Xilinx Answer #9464): 3.4 FPGA Express - Verilog concatenation with an addition
synthesized incorrect logic.

(Xilinx Answer #7242): 3.4 FPGA Express - FPGA Express inserts ILD for ILDX_1
instantiation.

XST

(Xilinx Answer #10573): 3.1i XST - VERILOG synthesis: XST hangs at 50% when
synthesizing a Verilog file.

(Xilinx Answer #10572): 3.1i XST - XST rejects a valid Verilog operator % (VLG__2008).

(Xilinx Answer #10571): 3.1i XST - Crashes with Dr. Watson error: "c00000fd (stack
overflow)" when "Add I/O buffers" is deselected.

(Xilinx Answer #10570): 3.1i XST - XST hangs after the line: "Extracting 1-bit register
for internal node."

(Xilinx Answer #10082): 3.1i XST/WebPACK - Project Navigator hangs while synthesizing
a HDL file and XST.EXE keeps on running.
AR# 10611
Date Created 12/08/2000
Last Updated 08/19/2002
Status Archive
Type General Article