AR# 10628: FPGA Compiler II - Re-timing (register balancing) does not appear to offer any improvement.
AR# 10628
FPGA Compiler II - Re-timing (register balancing) does not appear to offer any improvement.
Description
Keywords: register, balance, retime, re-time, FPGA, Compiler II
Urgency: Standard
General Description: What can I do if the re-timing function does not appear to offer any improvement in FPGA Compiler II?
Solution
1. Synthesize the design without I/O pads inserted. 2. Re-time the design during this synthesis run. 3. Read the resulting EDIF back into FPGA Compiler II. 4. Re-synthesize and write out the EDIF WITH I/O inserted.