AR# 10630


SimPrim, Timing Simulation - What is a "$width" violation, and how do I fix it? (VHDL, Verilog)


General Description:

What is a "$width" violation, and how do I correct it?


In back-annotated (timing) simulation, the timing information is taken into account when simulation is run using the SDF (standard delay format) file.

The "$width" message occurs when the pulse width of a specific signal is less than what is required for the device to be used. The format of the width message is as follows:

# ** Error: /path/to/xilinx/verilog/src/simprims/X_FF.v(30):

$width( negedge CLK:29138 ps, 100 ps );

# Time: 29248 ps Iteration: 0 Instance: /test_bench/u1/\U1/X_FF\

The first line of the error message points to the line in the simulation model that is giving the error.

The second line points to the signal name that is violating the minimum pulse width specification, and the time that it occurs.

The third line in the error message gives the actual simulation time at which the error is reported, and the instance in the structural (time_sim) design that is reporting the error.

Consult the device switching characteristics (available in the Data Book) to find out the minimum pulse width requirements and to ensure that the stimulus conforms to the specs.

AR# 10630
Date 12/15/2012
Status Active
Type General Article
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