The following error is reported:
"ERROR:Cpld:30 - The design requires too many resources to fit in the specified device."
What can I do to make my design fit into a particular device? How do I choose the best optimization settings for my design?
First, try the different optimization strategies. Each setting (balanced, density, speed) tells the fitter to try different partitioning styles in order to meet the appropriate goal. If you try these three strategies, and the design still does not fit, continue with the following suggestions.
(NOTE: For a description of terms and instructions on how to change the optimization settings, see Resolution #2.)
1. Determine why the design does not fit. To do this, review the <design>.rpt header and verify that the number of MCs and number of PTs are fewer than are allowed in the device targeted.
2. Once the mode of failure has been determined, attempt to correct the problem by changing the optimization settings accordingly:
- If the number of required MCs is greater than the number of available MCs, it can often be reduced with a higher P-Term limit.
- If the number of required PTs is greater than the number of available PTs, it may not be possible to fit the design. Either remove logic from the design, or target a larger part.
3. If the number of MCs and number of PTs required are both within the maximums and the design still does not fit, it is probably because the number of inputs to a function block exceeds that available. In this case:
- If the number of MCs/PTs is significantly under the device's limit, it may help to lower the P-Term limit, thereby increasing MC (without exceeding the device limit), and spreading input requirements across multiple function blocks.
- Reduce the Collapsing Input Limit to a value of about 14 -- this also serves the purpose of spreading input requirements across multiple function blocks.
- Increase the Function Block Input limit to 39 or 40.
4. Foldback NANDs should be enabled for designs. They will not generally hurt design performance unless a very large number of them are used.
- MC, Mcell: Macrocell
- PT, P-Term: Product Term
- Foldback NAND, FbNAND: NAND gates on the XPLA3 that will allow the output of one macrocell to be fed to the input of another.
- Collapsing P-Term Limit: Limits the number of P-Terms per equation
- Collapsing Input Limit: Limits the number of equations per macrocell
- Block Input Limit: Function Block fan-in limit
For more detailed explanations, please refer to the Optimization help menu (available at the same location as the settings, which are described below).
2. Where do I find the implementation settings?
In Project Navigator, right-click on "Implement Design" in the Process window, then select "Properties."
- The Optimizing Method (Balance/Density/Speed) is located under the Design tab.
- "Foldback NANDs", "Collapsing P-Term Limit", and "Collapsing Input Limit" are all located under the Advanced tab.