2. Support
  3. AR# 1071: XACTstep Libraries Guide: TS identifier in Mentor NOT limited to 01, 02, etc.
  4. AR# 10719: 3.1i SP6 NGDBuild - ERROR:OldMap:661- FDC symbol "symbol_name" (output signal=signal_name) the attribute RLOC ...

AR# 10719

3.1i SP6 NGDBuild - ERROR:OldMap:661- FDC symbol "symbol_name" (output signal=signal_name) the attribute RLOC ...

Description

Keywords: old, map, RLOC, symbol, FDC, DFF, FPGA Express, program, 4K, NGDBuild

Urgency: Standard

General Description:
When the following circumstances exist:

1. A design is run through stand-alone FPGA Express (the line "(program FPGA Express"
exists in your EDIF file); and
2. The FDC components are RLOC'ed

this error message will occur:

ERROR:OldMap:661 - FDC symbol "symbol_name" (output signal=signal_name) -
The attribute RLOC has been placed on the wrong type of symbol. Please
consult the "Attributes, Constraints, and Carry Logic" section of the Libraries
Guide for more information on legal parameters.

Translate (NGDBuild) does not pass the RLOC through the FDC properly. This error
was introduced in Service Pack 6.

Solution

1

Rename the following two directories to anything but these original names:

%XILINX%\fpga_express
%XILINX%\fpga_compiler_ii

2

Edit the EDIF file line:

(program "FPGA Express"

to

(program "UNKNOWN"
AR# 10719
Date 08/20/2002
Status Archive
Type General Article