General Description: When the following circumstances exist:
1. A design is run through stand-alone FPGA Express (the line "(program FPGA Express" exists in your EDIF file); and 2. The FDC components are RLOC'ed
this error message will occur:
ERROR:OldMap:661 - FDC symbol "symbol_name" (output signal=signal_name) - The attribute RLOC has been placed on the wrong type of symbol. Please consult the "Attributes, Constraints, and Carry Logic" section of the Libraries Guide for more information on legal parameters.
Translate (NGDBuild) does not pass the RLOC through the FDC properly. This error was introduced in Service Pack 6.
Rename the following two directories to anything but these original names: