2. Support
  3. AR# 1078: ModelSim (MXE, SE, PE) - How do I run a functional (behavioral) simulation with ModelSim stand-alone? (VHDL, Verilog)
  4. AR# 10781: 3.3.06i Virtex-E - Clock skew increases after upgrading to Service Pack 6

AR# 10781

3.3.06i Virtex-E - Clock skew increases after upgrading to Service Pack 6

Description

General Description:

After upgrading to Service Pack 6, large Virtex-E designs may exhibit

significantly increased clock skew as reported by static timing analysis.

Solution

This problem is scheduled to be fixed in the next 3.1i Service Pack

available at: http://support.xilinx.com/support/techsup/sw_updates.

The first service pack that will contain the fix is 3.1i Service Pack 7.

AR# 10781
Date 01/18/2010
Status Archive
Type General Article