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  3. AR# 10822: EXEMPLAR - How do I instantiate a triple-module redundancy (TMR) register for Virtex in Leonardo Spectrum?

AR# 10822

EXEMPLAR - How do I instantiate a triple-module redundancy (TMR) register for Virtex in Leonardo Spectrum?

Description

Keywords: TMR, triple, redundancy, module, register, Leonardo, Spectrum, Exemplar, Leo

Urgency: Standard

General Description:
The Virtex series contains high-reliability parts called Virtex "RadHard" parts (or Virtex QPro). These parts should be used for implementing triple-module redundancy (TMR). For information on targeting radiation hardened parts, please refer to (Xilinx Answer 12618).

In Virtex architecture, 3-state buffers are not pass transistors; rather, they are actually hardwired AND-OR logic structure. In the examples below, the TMR register is using the wired-OR capability to implement triple-module redundancy. These elements are cross-coupled to produce the same Boolean function as that needed for the majority vote circuit.

The FD cell can be replaced by any other logic. The important aspect of this circuit is that the routing pips are controlled by SRAM cells; a single fault in that cell will affect only the BUFT input and not the output itself. To upset this circuit, routing pips for more than one flip-flop should be upset.

Leonardo Spectrum's Xilinx/Virtex library does not have cells that can implement TMR capability. However, you can do this by creating your own TMR. For example, if TMR capability is needed for a register, this can be done relatively easily in a Virtex device.

Solution

1

Verilog example:

// Truth Table
// fd1 fd2 fd3 out
// 0 0 0 0
// 0 0 1 0
// 0 1 0 0
// 0 1 1 1
// 1 0 0 0
// 1 0 1 1
// 1 0 1 1
// 1 1 0 1
// 1 1 1 1

module tmr_reg (d_in, clk, q_buft);
input d_in, clk;
output q_buft;

reg reg1_out, reg2_out, reg3_out;

FD fd1 (.Q(reg1_out), .C(clk), .D(d_in));
FD fd2 (.Q(reg2_out), .C(clk), .D(d_in));
FD fd3 (.Q(reg3_out), .C(clk), .D(d_in));

BUFT buft1 (.I(reg1_out), .T(reg3_out), .O(q_buft));
BUFT buft2 (.I(reg2_out), .T(reg1_out), .O(q_buft));
BUFT buft3 (.I(reg3_out), .T(reg2_out), .O(q_buft));

endmodule // tmr_reg

2

VHDL example:

--Truth Table
--fd1 fd2 fd3 out
-- 0 0 0 0
-- 0 0 1 0
-- 0 1 0 0
-- 0 1 1 1
-- 1 0 0 0
-- 1 0 1 1
-- 1 0 1 1
-- 1 1 0 1
-- 1 1 1 1

library ieee;
use ieee.std_logic_1164.all;

entity tmr_reg is
port (d_in : in std_logic;
clk : in std_logic;
q_buft : out std_logic);
end entity;

architecture tmr_reg_arch of tmr_reg is

component FD is
port (D : in std_logic;
C : in std_logic;
Q : out std_logic);
end component;

component BUFT is
port (I : in std_logic;
T : in std_logic;
O : out std_logic);
end component;

signal reg1_out, reg2_out, reg3_out : std_logic;

begin

fd1 : FD port map
(D => d_in,
C => clk,
Q => reg1_out);

fd2 : FD port map
(D => d_in,
C => clk,
Q => reg_out2);

fd3 : FD port map
(D => d_in,
C => clk,
Q => reg_out3);

buft1 : BUFT port map
(I => reg1_out,
T => reg3_out,
O => q_buft);

buft2 : BUFT port map
(I => reg2_out,
T => reg1_out,
O => q_buft);

buft3 : BUFT port map
(I => reg3_out,
T => reg2_out,
O => q_buft);

end architecture;
AR# 10822
Date 09/18/2006
Status Archive
Type General Article
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