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AR# 10861

4.1i UniSim, SimPrim - Limitations of the CLKDLL and DCM simulation models for Virtex and Spartan-II devices (VHDL, Verilog)


Keywords: UniSim, SimPrim, CLKDLL, DCM, Virtex, Spartan-II, simulation, libraries

Urgency: Standard

General Description:
Current versions of the CLKDLL and DCM library models have limitations that are not present in hardware. This Answer Record describes these limitations.


Version 4.1i of the Xilinx software tools contains the following limitations in the CLKDLL and DCM simulation models:

VHDL and Verilog
1. The locked signal behaves inconsistently if the CLKIN signal is stopped and then restarted in the middle of a simulation run (i.e., after the DLL has initially started operating and has successfully LOCKED). The known behaviors are:
a) the LOCKED signal may toggle inconsistently if the CLKIN signal stops clocking for a period of time and starts clocking again
b) the LOCKED signal does not go low once CLKIN stops toggling
This problem is observed on all versions of the CLKDLL and DCM simulation models, and will be fixed in a future release of the Library tools. Xilinx recommends that you do not stop the CLKIN signal in simulation. However, if the CLKIN signal must be stopped, then pulsing the RESET signal on the CLKDLL/DCM ensures that the model restarts correctly.

2. In hardware, the CLKDLL/DCM models will restart successfully without requiring a manual reset if the CLKIN signal stops toggling for less than 100 ms. The simulation models do not have this functionality, and a fix is not currently scheduled.

3. In hardware, the minimum granularity of the DCM phase shift is the greater of the following two limiting factors:
a) the minimum phase shift step size = 1/256 x CLKIN_Period
b) the tap delay resolution (DCM_TAP); the specifications for DCM_TAP_MIN and DCM_TAP_MAX are available in the Virtex-II data sheet, Module 3 -> DCM Timing Parameters -> Miscellaneous Timing Parameters:

However, the simulation only supports the first factor. Therefore, do not check the tap delay resolution. For frequencies over 90 MHZ, the phase shift in simulation will be inaccurate (by a factor of picoseconds).

VHDL only
The LOCKED signal behaves incorrectly for some stimulus combinations when the VARIABLE or FIXED phase shifting modes are used in the DCM.
AR# 10861
Date 05/05/2004
Status Archive
Type General Article