2. Support
  3. AR# 1089: VERILOG-XL: Specifying multiple libraries in a Verilog simulation
  4. AR# 10898: 3.1i XST - XST output fails in simulation for designs that contain certain array constructs.

AR# 10898

3.1i XST - XST output fails in simulation for designs that contain certain array constructs.

Description

Keywords: simulation, fail, array, conv_integer, constant, V2, Virtex-II

Urgency: Standard

General Description:
XST generates incorrect logic (without any warning) due to an incorrect support of array
indices with the following form:

conv_integer (Signal) - Constant

For example, "T(conv_integer(Address) -1)" will fail.

This is due to the fact that XST considers an extra bit for the size of the expression
"conv_integer (Signal) - Constant"; therefore, it is generating incorrect address logic.

Solution

The problem is fixed in the latest 3.1i Service Pack available at:
http://support.xilinx.com/suport/techsup/sw_updates. The first
service pack containing the fix is 3.1i Service Pack 7.

AR# 10898
Date 08/19/2002
Status Archive
Type General Article