{SP1} (Xilinx Answer #9344): 3.1i Virtex MAP - Some eligible registers are not being packed into IOBs.
{SP1} (Xilinx Answer #9077): 3.1i Virtex MAP - ERROR:DesignRules:368 - Netcheck: Sourceless. Net $3I2/..... has no source.
NCDesign
{SP5} (Xilinx Answer #10156): 3.1i Virtex-E NCDesign - Software will not support IBUFG_LVDS inputs for XCV405E.
NGD2VER
{SP5} (Xilinx Answer #10302): 3.1i Virtex-E NGD2VER - time_sim.vhd file contains generic FACTORY_JF for X_CLKDLL2 module which is not in SimPrim model.
NGDANNO
{SP7} (Xilinx Answer #10904): 3.3i NGDAnno - Running NGDAnno with NGM file creates large delay on CLK port.
{SP7} (Xilinx Answer #10903): MTI Timing simulation - Possible setup violations are caused by NGDAnno not annotating delays between SRL16 and a flip-flop that are in the same slice.
NGDBUILD
{SP6} (Xilinx Answer #9573): 3.1i NGDBuild - Fatal-Error:Utilities:utilblist.c:234:1.4 MAX ELEMENT COUNT EXCEEDED.
{SP6} (Xilinx Answer #10223): 3.1i NGDBuild - XML Parser environment is incorrectly set up, preventing it from finding its text transcoding files.
{SP2} (Xilinx Answer #9380): 3.1i NGDBuild - ERROR:NgdBuild:393 - Could not find INST(S) 'GRP0' in design 'top'...
{SP1} (Xilinx Answer #9573): 3.1i NGDBuild - Fatal-Error:Utilities:utilblist.c:234:1.4 MAX ELEMENT COUNT EXCEEDED.
PACKAGE FILES
{SP5} (Xilinx Answer #10393): 3.1i Virtex-E Package Files - The BG560 package is now available for XCV400E and XCV600E.
{SP4} (Xilinx Answer #10259): 3.1i Virtex-II Package Files - New Virtex-II package files are included in 3.1i Service Pack 4.
{SP3} (Xilinx Answer #10030): 3.1i XC4000XL/XC4000XLA Package Files - Missing pins result in incomplete .pad file from PAR.
{SP3} (Xilinx Answer #10031): 3.1i XC4000XLA Package Files - The XC4085XLA BG352 package has bad pin out.
{SP3} (Xilinx Answer #10032): 3.1i Virtex Package Files - XV150 FG456 missing VCC pin J7 leading to incomplete .pad file.
{SP3} (Xilinx Answer #10037): 3.1i Spartan-II Package Files - x2s15 TQ144 package missing N.C. pins leading to incomplete .pad file.
{SP3} (Xilinx Answer #10050): 3.1i Spartan Package Files - Packages are missing some no connect pins, affecting .pad report.
{SP3} (Xilinx Answer #10051): 3.1i XC4000E Package Files - Several package files are missing pins, affecting the .pad file.
{SP3} (Xilinx Answer #10052): 3.1i Virtex Package Files - The Virtex CB228 package files are missing pins, affecting the .pad report.
{SP2} (Xilinx Answer #9711): 3.1i Package Files - P39 in XC2S50 PQ208 package is listed as VCCINT instead of NC.
{SP2} (Xilinx Answer #9710): 3.1i Spartan-II Package Files - X2S200 FG456 and BG352 package files are missing VCCINT pins.
{SP2} (Xilinx Answer #3149): 3.1i Package Files - Spartan XCS10 TQ144 does not have the TMS pin bonded.
PAR
{SP7} (Xilinx Answer #10872): 3.1i Virtex-II PAR - PAR hangs while routing PWR/GND nets in a Virtex-II design.
{SP7} (Xilinx Answer #10705): 3.1i Virtex-II PAR - PAR hangs while routing PWR/GND nets in a Virtex-II design.
{SP7} (Xilinx Answer #10870): 3.1i Virtex-II PAR - Placer not honoring LOC constraints on slices.
{SP7} (Xilinx Answer #10868): 3.1i Virtex-II - PAR runs out of memory on Virtex-II designs with area groups.
{SP7} (Xilinx Answer #10505): 3.1i Virtex-II PAR - Placer unable to handle certain legal DPRAM configurations.
{SP6} (Xilinx Answer #10561): 3.1i Virtex-E PAR - Placer rejects placement of slices containing F5/F6 MUX.
{SP6} (Xilinx Answer #10566): 3.1i Virtex PAR - Placer places two signals on one SIGPIN.
{SP5} (Xilinx Answer #10392): 3.1i Virtex PAR - FATAL_ERROR:Route:basrtsanity.c:168:1.7.28.1 - Process will terminate.