UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 10903

MTI Timing Simulation - Setup violations are caused by NGDAnno not annotating delays between an SRL16 and a FF that are in the same slice.

Description

Keywords: MTI, Timing, Simulation, Setup, SRL16

Urgency: Standard

Problem Description:
MTI timing simulation may get setup violations on a flip-flop that was driven by an SRL16
if the FF and the SRL16 are put inside the same slice.

Solution

This problem is fixed in the latest 3.1i Service Pack available at:
http://support.xilinx.com/support/techsup/sw_updates. The first
service pack containing the fix is 3.1i Service Pack 7.
AR# 10903
Date Created 01/31/2001
Last Updated 11/07/2004
Status Archive
Type General Article