AR# 10909: 6.1i CORE Generator - Verilog behavioral simulation on core reports a "Too few port connections" warning
6.1i CORE Generator - Verilog behavioral simulation on core reports a "Too few port connections" warning
During the Verilog behavioral simulation of a design with cores from CORE Generator, you might receive warning messages similar to following. (These are from the MTI simulator, and might differ slightly for other simulators.) Here is the exact warning message as seen in MTI, EE/PE 5.4c version:
This problem appears only in Verilog behavioral simulation, and these warnings occur for two reasons:
1. Your core is not using all the optional ports, but the Verilog behavioral models have all the ports listed in the file.
2. Your core uses another core (e.g., Async FIFO uses Dist Mem or Block Mem); therefore, the behavioral models have instantiation of sub-cores, and the instantiation does not list all the ports for the sub-cores.
These are simply warning messages and can be safely ignored.
If many warnings are reported and they are too numerous to ignore, a possible solution is to drive constants onto unused input ports, and leave unused output ports unconnected.
CORE Generator software changes are being made to address the first issue. CORE Generator will write the instantiation file or wrapper file to list all the unused ports as well. This change is expected in the first IP update of the 4.1i software.
To address the second issue, changes are also being made to the individual Verilog behavioral models. However, due to the high number of existing cores, these will be fixed only on a case-by-case basis as the problems arise.
If you are using the latest version of the core, and receive the "Too Few Port connections" warning, please report this to the Xilinx hotline (1-800-255-7778) and file a CR for that particular core. Please provide the complete warning messages from your simulator log file and the CORE Generator ".xco" file; this will help us to identify the Verilog models with the problem.