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  3. AR# 1095: Xchecker Cable: Can the Xchecker cable be used to program via JTAG Programming? Where is TDO?
  4. AR# 10956: 5.1i CORE Generator - D_IP2: The Pipelined Divider v2.0 latency is incorrect

AR# 10956

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5.1i CORE Generator - D_IP2: The Pipelined Divider v2.0 latency is incorrect

Description


General Description:

The Pipelined Divider v2.0 latency does not match the latency described by the data sheet.

Solution

The data sheet of the Pipelined Divider v2.0 is incorrect. In the "Latency" table, the columns for "Signed" and "Fractional" should be switched.

AR# 10956
Date 07/28/2010
Status Archive
Type General Article
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