When I use FPGA Express to synthesize VHDL code from System Generator, the following error occurs during synthesis:
"Error: NgdBuild:201 - An EDIF value has exceeded the maximum string limit of 500 characters..."
This error can occur when FPGA Express is used to synthesize System Generator VHDL and the design contains a number of hierarchy levels. Currently, FPGA Express is not supported as a synthesis tool to be used with System Generator.
To work around this problem, change the design so that it has fewer levels of hierarchy, or use a supported synthesis tool such as Synplicity's Synplify or Exemplar Spectrum.