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AR# 10980

System Generator for DSP - What does it mean that System Generator is "bit-true" and "cycle-true"?


General Description: 

What does Xilinx System Generator mean when it says it supports "bit-true" and "cycle-true" modeling of hardware?


Simulink is an event-driven simulator for dynamical systems, including continuous time and space systems defined via state space equations (i.e., differential equations) and discrete time and discrete space (countable, and for all intents and purposes, finite index sets). The latter is significant because it allows System Generator to model the evolution of hardware over time. This is important because, in theory, you can understand the bit and cycle behavior of the generated hardware (VHDL) from Simulink.  


Signals in System Generator are represented as (arbitrary precision) fixed-point data; in hardware, this corresponds to standard logic vectors. If you examine a System Generator signal in Simulink, its fixed point value will consist of the same bits as the corresponding bits of the standard logic vector in hardware. This is why System Generator is "bit-true."  


In addition to the fixed-point value, every System Generator signal is sampled and has an associated sample period. If you examine a signal in Simulink (e.g., with a Simulink Scope block), you will see that transitions occur only at multiples of the sample period for the block that drives the signal. In the hardware generated by System Generator, the corresponding standard logic vector is driven by a block that is clocked (or if combinational, has an "inherited" clock period from its inputs) at a particular clock rate.  


The corresponding sample period in Simulink is guaranteed to be a multiple of the hardware clock period. At the clock transitions that correspond to sample period multiples, the bits in the standard logic vector (hardware) match the fixed point data in the Simulink signal (software). This is why System Generator is "cycle-true."  


Sometimes one refers to models that are bit-true, but not cycle-true. Whatever that may mean, with System Generator, there is no ambiguity: the bits in a standard logic vector are identical to the bits in the corresponding fixed-point System Generator Simulink signal at the hardware clock transitions that correspond with multiples of the Simulink sample period.

AR# 10980
Date 05/14/2014
Status Archive
Type General Article