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3.x FPGA Express - When I use the `include statement in Verilog files, relative or absolute files are not recognized.
Keywords: 3.1i, FPGA Express, fe_shell, Verilog, include, relative, paths
FPGA Express will not recognize absolute or relative paths while using the
`include statement in Verilog files. Examples of this are:
You must have all of the Verilog files in the same directory so that the `include
statement will look like:
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